Generation of interface states by hot hole injection in MOSFET's

The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO2interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

Enhanced degradation in polycrystalline silicon thin-filmtransistors under dynamic hot-carrier stress

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G_{m max}) in static stress, G_{m max} in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Interface traps at high doping drain extension region insub-0.25-μm MOSTs

A huge bulk (or drain) current I_b (or I_d) peak versus gate voltage was observed for the 0.25-μm or sub-0.25-μm metal-oxide-semiconductor field effect transistors (MOSTs) with high doping concentration source/drain extension, when the drain-bulk p-n junction is forward biased. This current is increased under Fowler-Nordheim (FN) or channel hot carrier (CHC) stress and is identified as thermal-trap-tunneling electron current at the drain extension-gate overlap region. It is extremely sensitive that one interface trap will induce 0.1 pA current increment of peak I_b (or I_d)     

Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.     

Effect of hot-carrier injection on n- and pMOSFET gate oxideintegrity

N- and pMOSFETs with 9-nm gate oxide are compared. Injected hot holes are about 100 times as effective as electrons at 10.5 MV/cm of oxide field in causing oxide breakdown. Gate current in nMOSFETs under stress conditions is due to holes and electrons. The gate current in pMOSFETs is about 1000 times as large, but solely due to electrons. PMOSFETs can tolerate 1000 times more charge injection than nMOSFETs, but not more drain current stress     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

A thorough study of quasi-breakdown phenomenon of thin gate oxidein dual-gate CMOSFET's

The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO₂ interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve V_g, I_sub, I_sd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of I_sub(I_sd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate     

Electrical characterization and reliability of double-doped drain MOS transistors compatible with an EEPROM process

Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manufactured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at V_ds = 10 V, V_gs = 5 V. The observed degradation seems to be mainly due to acceptor-type interface state creation near the drain junction.     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Retention characteristics of hole-injection-type EEPROM

The retention characteristics of FAMOS-type EEPROM using avalanche injection of holes for ERASE operation were analyzed. The avalanche-injected holes into the SiO2gate oxide are likely to be trapped at the defects in the gate oxide before arriving at the floating gate. Some samples show that the threshold-voltage shift due to trapped holes versus the threshold voltage shift due to the total holes injected into the oxide comes up to 80 percent. The retention characteristics of trapped holes are poor. By detrapping these holes, the drain voltage of a FAMOS-type device is increased. The resultant acceleration of the unintentional writing due to the channel current-induced hot electrons may be a dominant factor in the retention characteristics.     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Random telegraph signals in deep submicron n-MOSFET's

Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained both by number and mobility fluctuations due to single electron trapping in the gate oxide. The role of the type of the trap (acceptor or donor), the distance of the trap from the Si-SiO₂ interface, the channel electron concentration (which is set by the gate bias) and the electron mobility (which is affected by the drain voltage) is demonstrated. The effect of capture and emission on average electron mobility is demonstrated for the first time. A simple theoretical model explains the observed effect of electron heating on electron capture. The mean capture time depends on the local velocity and the nonequilibrium temperature of channel electrons near the trap. The difference between the forward and reverse modes (source and drain exchanged) provides an estimate of the effective trap location along the channel