A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

一款适用于WCDMA标准的大动态范围SiGe HBT可变增益放大器设计

第三代移动通信标准WCDMA要求放大器增益可调,并且增益动态范围较大.根据这一要求给出了一种基于SiGe HBT具有高动态范围的可变增益放大器(VGA)设计.放大器为三级级联结构,第一级为输入缓冲级,第二级为增益控制级,最后为放大级.VGA的增益控制通过调整第二级的偏置实现.VGA在1.95 GHz频率下,在0～2.7 V增益控制电压变化下,具有44 dB增益变化范围,最大增益49 dB.在最大增益处最小噪声系数为2.584 dB,输入输出电压驻波比低于2,性能良好.     

A low-distortion CMOS IF VGA with linear-in-dB control and temperature compensation

A CMOS intermediate-frequency (IF) variable-gain amplifier (VGA) is presented in this paper. A transconductance linearization scheme is proposed for the VGA core based on a signal-subtracting structure to achieve low distortion. Temperature-independent decibel-linear gain control characteristic is achieved by an exponential voltage generator based on transfer characteristics of differential pair. The whole VGA, including a highly-linear output stage, is fabricated in 0.25 μm CMOS technology. Measurements show that the VGA provides a total gain control range of 43 dB with less than 1.2 dB error over 0–80°C, and a constant 3-dB bandwidth of 100 MHz. The third-order intermodulation (IM3) distortion at differential output of 2 V_PP is better than −55 dB. The VGA dissipates 22.6 mA averagely from 3.3 V supply, and occupies approximately 0.53 mm².     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

GaAs Monolithic Low-Power Amplifiers with RC Parallel Feedback (Short Paper)

GaAs monolithic broad-band low-power-dissipated amplifiers with inductive/resistive load and RC parallel feedback circuits have been developed. An inductive load amplifier provides a gain of 8 dB, a 3-dB bandwidth of 2.5 GHz, and a noise figure of 2.7 dB at 1 GHz with less than + 1-V supply voltage and very low-power dissipation of 20 mW. A resistive load two-stage amplifier provides a gain of 15 dB and a 3-dB bandwidth of 2 GHz. Input and output reflection coefficients at 1 GHz are -13 dB and -21 dB, respectively.     

A low-power low-noise accurate linear-in-dB variable-gain amplifierwith 500-MHz bandwidth

A linear-in-dB variable-gain amplifier (VGA) using a pre-distortion circuit to generate the gain-control signal is fabricated in a BiCMOS process with f_T=20 GHz. The VGA comprises two cascaded stages of signal-summing VGA and has a variable-gain range of over 70 dB. It can operate at up to 500 MHz and dissipates 36 mW from a 3-V supply. A noise figure of below 5 dB and IIP3 of over -38 dBm at 43-dB gain were obtained. The VGA achieved a gain error of less than 2 dB over 70-dB gain range, and it occupies approximately 1 mm². The VGA is applicable to future code division multiple access (CDMA) receivers     

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A fully balanced CMOS Variable Gain Amplifier (VGA) based on current-mode techniques suitable for high frequency applications and large signals is presented. The VGA consists of an analog multiplier, current gain stages, and resistive loads. A frequency compensation scheme based on a capacitive feed-forward technique increases the bandwidth by more than 60%. Common-Mode Feed-Forward (CMFF) techniques are used to minimize dc offsets. The gain can be programmed from 0 to 42 dB with ?3 dB bandwidth greater than 270 MHz; a gain calibration scheme for precise gain control applications is included. The Third Harmonic Distortion (HD3) is less than ?55 dB for differential input and output voltages of 1 V_pk-pk. The VGA was fabricated in a standard 0.35 μm CMOS process, and consumes around 54 mW from a single power supply of 2.7 V.     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

具有温度补偿及dB线性增益控制的单级宽范围CMOS可变增益放大器

提出了一种新颖的宽范围CMOS可变增益放大器结构.利用可变跨导和新颖的可变输出电阻,基于单独可变增益级的放大器可提供80dB的宽范围调节.同时控制电路的设计完成了温度补偿及dB线性增益特性,实现在整个温度及增益调节范围内绝对增益误差小于±1.5dB.基于0.25μm CMOS工艺验证表明,放大器可提供64.5dB的增益变化范围,其中dB线性范围为55.6dB.输入1dB压缩点为-17.5到11.5dBm,3dB带宽为65MHz到860MHz,2.5V电源供电下功耗为16.5mW.     

Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications

A high frequency CMOS variable gain amplifier (VGA) employing a new gain stage cell is proposed. A design technique based on the proposed VGA enables enhancement of its operating frequency up to about 350 MHz with a gain control range of 84 dB. The power consumption of the VGA implemented using a 0.18 /spl mu/m CMOS standard process is about 3 mA at 1.8 V supply voltage.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A monolithically integrated HEMT-HBT low noise high linearityvariable gain amplifier

We report on a 1-6 GHz HEMT-HBT three-stage variable gain amplifier (VGA), which is realized using selective molecular beam epitaxy (MBE). The VGA integrates an HEMT low noise amplifier with an HBT analog current-steer variable gain cell and output driver stage to achieve a combination of low noise figure, wide gain control, and high linearity. The HEMT-HBT VGA MMIC obtains a maximum gain of 21 dB with a gain control range >30 dB, a minimum noise figure of 4.3 dB, and an input IP3 (IIP3) greater than -4 dBm over 25 dB of gain central range. By integrating an HEMT instead of on HBT preamplifier stage, the VGA noise figure is improved by as much as 2 dB compared to an all-HBT single-technology design. The HEMT-HBT MMIC demonstrates the functional utility and RF performance advantage of monolithically integrating both HEMT and HBT devices on a single substrate     

一种S波段平衡式限幅低噪声放大器的设计

介绍了一种小型化平衡式限幅低噪声放大器。该放大器采用Lange桥平衡结构,在实现低噪声的同时,保证了小电压驻波比;在3.0～3.5GHz频带内,噪声系数小于1.3dB,输入输出驻波系数小于1.3,增益大于27dB,平坦度±0.6dB以内,输出1dB压缩点大于12dBm。该放大器能够承受最大5W的连续波功率输入,且大功率输入时的驻波系数小于1.3。     

A ± 0.75-V Compact CMOS Class-AB Current-Mode Exponential Variable Gain Amplifier

In this brief, a novel class-AB implementation of a current-mode exponential variable gain amplifier (VGA) is presented. The VGA is based on a novel current amplifier circuit implemented by multicoupled MOS translinear loops operating in strong inversion and saturation. The gain is conveniently configured for performing a pseudo-exponential approximation leading to a very compact design since an extra multiplier is not needed. Moreover the VGA can operate with very low voltage and power efficiency. Measurement results from a fabricated prototype in a 0.5-mum n-well CMOS technology reveal gain control up to 12 dB with errors less than plusmn0.5 dB and power consumption of 375 muW for a supply voltage of plusmn0.75 V.     

A broadband linear-in-decibel variable gain amplifier with low gain error

A new circuit architecture for broadband digitally controlled variable gain amplifier (VGA) is introduced in this paper. The gain of the VGA is controlled precisely by using a resistor ladder attenuator and a closed-loop fine gain control block together. The bandwidth of the VGA is extended by applying a compensation technique in the fine gain control block. Implemented in 0.13-μm CMOS technology, the proposed VGA demonstrates a decibel-linear gain range of 24 dB (0–24 dB) with a gain step of 0.1 dB, a gain error <0.08 dB, a maximum input-referred third-order intercept point (IIP3) of 22.8 dBm, and a 3-dB bandwidth of 600 MHz.     

A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level.     

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

电荷泵型LED驱动器的CMOS误差放大器设计

结合电荷泵型LED驱动器的工作要求,从减小输出电压纹波、稳定输出电压出发,设计了一款误差放大器。该误差放大器具有较大的工作电压范围,使电荷泵型LED驱动器高效率低噪声工作。基于CHRT0．35μm CMOS MIXED SIGNAL TECHNOLOGY进行仿真,结果表明,在2．7～5V工作电压范围内,开环电压增益约等于72dB,相位裕度约等于65°,单位增益带宽约等于4．6MHz,共模抑制比CMRR约等于113dB,电源抑制比PSRR约等于100dB。     

High efficiency, wide dynamic range variable gain and poweramplifier MMICs for wideband CDMA handsets

A linearized variable gain amplifier (VGA) and a two-stage power amplifier (PA) MMIC were developed for 1.95-GHz wideband CDMA (W-CDMA) handsets application. A complete PA block with power control ability was obtained by cascading the VGA with the PA. The linearized VGA consists of a predistorter (PD) integrated with a conventional VGA, performing dual function for achieving high linearity power control, as well as reducing output distortion level of the following PA. With the use of predistortion, the P_out and power added efficiency (PAE) of the PA block improved from 27.5 dBm and 39.8% to 28.5 dBm and 44.8%, respectively, measured at -35 dBc adjacent channel leakage power ratio (ACPR). Under power control operation, the control range of the PA block increased from 23.6 dB to 31.2 db, and ACPR reduction of over 10 dB was achieved with the use of linearized VGA