可降低BGA器件费用的新型基片技术

StMT(Surface Mount Technology表面贴装技术)进入90年代以来,走向了成熟的阶段。但随着电子产品向便携式、小型化、网络化和多媒体化方向的迅速发展,对电子组装技术提出了更高的要求。新的高密度组装技术不断涌现,其中BGA(Ball Grid Array球栅阵列封装)就是一项已经进入实用化阶段的高密度组装技术。 一、高性能高价位BGA器件 BGA器件,比起以往所采用的封装方式来说,具有能够容纳大量引脚的能力,以及具有较小的封装尺寸、良好的性能、较高的板装配量和较高     

BGA技术与质量控制

BGA(Ball Grid Array球栅阵列封装)是一项已经进入实用化阶段的高密度组装技术。本文将就BGA器件焊点的质量控制作一介绍。BGA检测中存在的问题 目前,对以中等规模到大规模采用BGA器件进行电子组装的厂商,主要是采用电子测试的方式来筛选BGA器件的焊接缺陷。在BGA器件装配期间     

球栅阵列器件及其清洗

球栅阵列技术已经激起了电子行业的人们强烈的兴趣。随着人们的目光愈来愈多地关注于BGA器件的组装的时候，对BGA器件进行组装时所产生的清洗和干燥的问题受到了人们广泛的关注，各种各样的BGA器件和焊膏需要采用合适的清洗处理方法。     

BGA表面安装工艺简注

随着表面安装技术(SMT)的飞速发展,人们越来越重视BGA的工艺研究。BGA是一种球栅阵列的表面封装器件,它的引脚成球形阵列状分布在封装的底面,因此,它可以有较大的脚间距和较多的引脚数量,这对电路设计者和电路生产组装者来讲是一个福音。 一、BGA的工艺特点 BGA作为一种新的SMT封装形式是从PGA演变而来的,它有自己的工艺特点,其主要优点如下:     

基于BGA技术的多功能LC滤波器三维组装设计

本文提出了一种基于BGA（ball grid array）球栅阵列技术的多功能LC滤波器组装设计方法。该方法利用BGA阵列连接,实现多个基板的三维集成互联组装。将电感磁芯等元件置于顶层基板上,电容和芯片等元器件置于底层基板上。同时对BGA基板三维组装和元器件安装工艺技术进行研究和分析,提供了基于BGA技术实现的小型化多功能LC滤波器解决方案。     

BGA／CSP的2000年标准化动态

伴随电子工业继续向着小型化的方向发展,我们必须认识到没有标准经,最新设计的BGA／CSP组件不可能以较低的成本及时地进入常用封装器件的角色。基本的常用包装包括：管式、托盘式、卷带、测试插座和组装板。标准化是力图使常用器件供应商去满足现在发展起来的BGA／CSP工业化的应用要求。缺乏标准会导致客户在供应商提供产品范围非常有限的情况下产品最终的成本提高,最主要的是浪费了时间,这在半导体市场生命周期很短的情况下是最严重的成本支出。最新的世界半导体技术指南1999版比以前的指南更进一步降低了组件的封装成本,一种新的封装形式组件若成本过高或上市时间过晚都将被市场所淘汰。标准经工作不仅要在局部区域内开展,像JEDEC（美国）和EIAJ（日本）,而且要考虑更高水平的发展。在封装领域的最高权威是IEC（国际电子技术委员会）TC－47D,它减少了在未限制用户选择性能更加可靠而价格更加低廉的封装组件时组件封装形式可能出现的不统一。对于BGA封装的介绍可以为电子产品生产提供一种封装形式的概念,使他们只管利用旧的贴片设备去生产而不用担心组件封装周围的引线共面性不良或发生变形。BGA封装的组件使生产不必考虑组装窄间距芯片（0．50、0．40、0．30mm或更小）带来的麻烦。BGA／CSP组件的缺点在于它是阵列方式的封装结构,它们在焊球的间路、焊点的直径及组件上焊球的数量有很大的变化。一个CSP可以看作是一个更薄、更小、焊球间距更窄的BGA。这种概念上较大的伸缩性使得对其严格标准化的需求比对周围带有引线封装的器件更为迫切。     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件(3D-MCM).采用层压、开槽等工艺获得埋置式高密度多层有机(FR-4)基板,通过板上芯片(COB)、板上倒装芯片(FCOB)、球栅阵列(BGA)等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术(SMT)兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成r融合多种互连方式3D-MCM封装结构.埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题.对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性.电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

国际电子工业联接协会出版IPC-7095B版标准

IPC-国际电子工业联接协会出版了IPC-7095B版标准,即《BGA的设计及组装工艺的实施》。实施球栅阵列（BGA）和细间距BGA（FBGA）技术对设计、组装、检验和返修人员带来了特有的挑战。IPC-7095B为目前正在使用BGA或者有意转向采用面积阵列封装设计的公司提供了非常实用的信息。目前BGA封装所用合金及将其连接到印制板连接盘上所用的焊料合金正在经历着从有铅转向无铅的巨大变革,     

用于高速光电组件的光焊球阵列封装技术

本文介绍了用于高速光电组件的表面安装型焊球阵列(BGA)封装技术。     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost     

Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

Near-CSP plastic ball grid array

The mold array process plastic ball grid array continues to demonstrate progress as a cost-effective, medium to high performance electronics package. Highly manufacturable and reliable solutions to the challenges of molding up to several hundred packages at one time as well as subsequent singulation of the packages have been found. JEDEC moisture performance at up to Level 1 with 220°C reflow temperatures has been qualified for production. Thermal performance remains critically dependent on die size, package size, and motherboard construction.     

Thermal design of a broadband communication system with detailed modeling of TBGA packages

This paper presents a thermal modeling of a broadband network communication box partitioned into two stacked modules. A printed circuit board (PCB) is inside each module where an array of 16 tape ball grid array (TBGA) packages is surface mounted to the PCB. The TBGA package dissipates 6 W power each. In addition, 12 W of power is dissipated from four plastic ball grid array (PBGA) packages on the PCB. Pin-fin heat sinks are attached to the TBGA packages using silica-filled epoxy to enhance heat dissipation. Pin-fin heat sinks are also attached to the PBGA packages. Two exhaust fans are mounted at the flow exit to draw ambient air into the system at approximately 200 linear feet per minute (LFM) of velocity. The full Navier–Stokes equations for airflow are solved to simulate the forced convection cooling in the electronic module. Buoyancy effect was considered in the numerical model by incorporating Boussinesq-approximation. The TBGA packages are modeled in detail in order to obtain the package junction temperatures for system reliability evaluation and thermal design optimization. Detailed models of the attached pin-fin heat sinks and the epoxy interfaces are also utilized in this study. Compact heat sink model composed of a base plate and a resistance fluid volume is applied to model heat dissipation from the heat sinks attached to the four PBGA packages. System fan curve is used to simulate the fan operating conditions. The effect of changing system thermal design on the TBGA package junction temperatures as well as the hydraulic operating conditions of the system fans are examined and reported herein. The effect of radiation heat transfer is also examined. The importance of detailed modeling of the high power TBGA packages is demonstrated in this study. Simulation results were compared with JEDEC thermal test data under similar conditions of airflow.     

用于ASIC的PGA外壳设计与工艺

本文叙述了用于ASIC的高密度封装之———PGA外壳的设计和工艺方法。     

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages.A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.     

全铜通孔柔性LED封装热学性能仿真分析

柔性基板封装(COF)是一种新型LED封装形式。本研究在柔性基板中的高分子绝缘层(PI)中添加全铜通孔,通过有限元仿真分析全铜通孔对LED封装热学性能的影响。研究结果表明：在柔性LED封装中,PI层热阻最大,是导致芯片结温高的主要因素。PI层中全铜通孔的添加使PI层热阻大幅降低,显著提升LED封装的垂直散热能力。基于仿真计算结果,建立了PI层中添加全铜通孔数量与LED封装热阻间的对应关系。针对本研究中的封装结构,采用8*8 的全铜通孔阵列对LED封装的热学性能提升效果显著。     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

激光重熔在钎料凸点成形中的应用

激光由于具有高能量输入密度以及可局部加热的优点而在面阵列电子封装钎料凸点成形中具有潜在的优势，介绍了激光重熔在面阵列封装钎料凸点成形中的研究进展，并且对PBGA共晶钎料球激光重熔进行了工艺研究，研究结果表明；采用合适的激光输入能量可以在非常短的时间内获得表面质量光滑的钎料凸点。