A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

A Dual-Band Self-Oscillating Mixer for -Band and -Band Applications

A self-oscillating mixer that employs both the fundamental and harmonic signals generated by the oscillator subcircuit in the mixing process is experimentally demonstrated. The resulting circuit is a dual-band down-converting mixer that can operate in $C$ -band from 5.0 to 6.0 GHz, or in $X$-band from 9.8 to 11.8 GHz. The oscillator uses active superharmonic coupling to enforce the quadrature relationship of the fundamental outputs. Either the fundamental outputs of the oscillator or the second harmonic oscillator output signals that exists at the common-mode nodes are connected to the mixer via a set of complementary switches. The mixer achieves a conversion gain between 5–12 dB in both frequency bands. The output 1-dB compression points for both modes of the mixer are approximately $-{hbox{5 dBm}}$ and the output third-order intercept point for $C$ -band and $X$ -band operation are 12 and 13 dBm, respectively. The integrated circuit was fabricated in 0.13-$mu {hbox{m}}$ CMOS technology and measures ${hbox{0.525 mm}}^{2}$ including bonding pads.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13-$mu$m CMOS Technology

A compact and broadband 0.8–77.5-GHz passive distributed drain mixer using standard 0.13-$mu$ m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of ${hbox{5.5}} pm {hbox{1}}$ dB from 0.8 to 77.5 GHz with a compact size of 0.67$,times,$ 0.58 mm$^{2}$ . The output 1-dB compression point is ${-}{hbox{8.5}}$ dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A 0.1–5 GHz Cryogenic SiGe MMIC LNA

In this letter, the design and measurement of the first SiGe integrated-circuit LNA specifically designed for operation at cryogenic temperatures is presented. At room temperature, the circuit provides greater than 25.8 dB of gain with an average noise temperature $(T_{e})$ of 76 K $(NF=1 {rm dB})$ and $S_{11}$ of $-$ 9 dB for frequencies in the 0.1–5 GHz band. At 15 K, the amplifier has greater than 29.6 dB of gain with an average $T_{e}$ of 4.3 K and $S_{11}$ of $-$14.6 dB for frequencies in the 0.1–5 GHz range. To the authors' knowledge, this is the lowest noise ever reported for a silicon integrated circuit operating in the low microwave range and the first matched wideband cryogenic integrated circuit LNA that covers frequencies as low as 0.1 GHz.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 $mu$ m CMOS

A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 $mu$m CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of ${-}$4.45 dBm and a conversion gain of ${-}$ 0.45 dB at input frequency of 27.1 GHz with an input power of ${-}$4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm$, times ,$0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.      

70 GHz Folded Loop Dual-Mode Bandpass Filter Fabricated Using 0.18 $mu$ m Standard CMOS Technology

This letter presents the design and implementation of a 70 GHz millimeter-wave compact folded loop dual-mode on-chip bandpass filter (BPF) using a 0.18 $mu$m standard CMOS process. A compact BPF, consisting of such a planar ring resonator structure having dual transmission zeros was fabricated and designed. The size of the designed filter is 650$,times,$ 670 $mu$ m$^{2}$ . Calculated circuit model, EM simulated and measured results of the proposed filter operating at 70 GHz are shown in a good agreement and have good performance. The filter has a 3-dB bandwidth of about 18 GHz at the center frequency of 70 GHz. The measured insertion loss of the passband is about 3.6 dB and the return loss is better than 10 dB within the passband.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

A 22–29-GHz UWB Pulse-Radar Receiver Front-End in 0.18-$mu{hbox{m}}$ CMOS

The design of a CMOS 22–29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-$mu{hbox{m}}$ CMOS process, the RX front-end chip occupies a die area of 3 ${hbox{mm}}^{2}$. On-wafer measurements show a conversion gain of 35–38.1 dB, a noise figure of 5.5–7.4 dB, and an input return loss less than $-$14.5 dB in the 22–29-GHz automotive radar band. The phase noise of the constituent QVCO is $-$107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.      

A 2–40 GHz Active Balun Using 0.13 $mu{rm m}$ CMOS Process

A 2 to 40 GHz broadband active balun using 0.13 $mu{rm m}$ CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of ${0} pm{1}~{rm dB}$, with the amplitude imbalances below 0.5 dB and the phase differences of ${180} pm {10} ^{circ}$ from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm $times,$ 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

High Microwave-Noise Performance of AlGaN/GaN MISHEMTs on Silicon With Gate Insulator Grown by ALD

High microwave-noise performance is realized in AlGaN/GaN metal–insulator semiconductor high-electron mobility transistors (MISHEMTs) on high-resistivity silicon substrate using atomic-layer-deposited (ALD) $hbox{Al}_{2}hbox{O}_{3}$ as gate insulator. The ALD $hbox{Al}_{2}hbox{O}_{3}/hbox{AlGaN/GaN}$ MISHEMT with a 0.25- $muhbox{m}$ gate length shows excellent microwave small signal and noise performance. A high current-gain cutoff frequency $f_{T}$ of 40 GHz and maximum oscillation frequency $f_{max}$ of 76 GHz were achieved. At 10 GHz, the device exhibits low minimum-noise figure $(hbox{NF}_{min})$ of 1.0 dB together with high associate gain $(G_{a})$ of 10.5 dB and low equivalent noise resistance $(R_{n})$ of 29.2 $Omega$. This is believed to be the first report of a 0.25-$muhbox{m}$ gate-length GaN MISHEMT on silicon with such microwave-noise performance. These results indicate that the AlGaN/GaN MISHEMT with ALD $hbox{Al}_{2}hbox{O}_{3}$ gate insulator on high-resistivity Si substrate is suitable for microwave low-noise applications.      

Analysis, Design, and $X$-Band Implementation of a Self-Biased Active Feedback $G_{m}$ -Boosted Common-Gate CMOS LNA

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for $g_{m}$ boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without $g_{m}$ boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-$mu$ m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of ${-}$ 11.3 dBm, a return loss of ${-}$ 17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 $mu$m $^{2}$.      

A 30–100 GHz Wideband Sub-Harmonic Active Mixer in 90 nm CMOS Technology

This letter presents a 30–100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits ${-}{hbox{1.5}} pm {hbox{1.5}}$ dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm$^{2}$. The OP$_{1 {rm dB}}$ of the mixer is ${-}$ 10.4 dBm and ${-}$9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.      

A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-$Q$ above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- $Q$ above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point $({rm IP}_{{-}1~{rm dB}})$ is ${- 9.5}~{rm dBm}$ and the input referred third-order intercept point $(P _{rm IIP3})$ is ${+ 2.25}~{rm dBm}$. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.