Intermetal dielectric deposition by electron cyclotron resonance chemical vapor deposition (ECR CVD)

Advanced microprocessor and logic devices require multiple levels of metal to interconnect the many transistors that form them. Three-, four-, and five level metallization schemes are in production. The insulating material between these layers must fill very narrow gaps, without voids or seams, with a high quality dielectric, and must allow for subsequent global planarization such as chemical mechanical polishing (CMP). These requirements can be met with ECR CVD of silicon dioxide. ECR deposits high quality SiO₂ dielectric in a single wafer process that fills gaps 0.3 μm and smaller at aspect ratios 3:1 and greater on 200 mm wafers. Its electrical, optical, and chemical properties approach those of thermal oxide.     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

Comparison of AlGaN/GaN MSM Varactor Diodes Based on HFET and MOSHFET Layer Structures

In this letter, the performance of AlGaN/GaN-based metal-semiconductor-metal (MSM) varactor diodes based on HFET and MOSHFET layer systems is investigated. Passivated HFET MSM devices are coated with a 10-nm-thick SiO₂ layer between the electrodes; in MOSHFET-based diodes, this layer is also used as an insulator underneath the gate. Device fabrication uses standard HFET fabrication technology, allowing easy integration in monolithic microwave integrated circuits. Devices with different electrode geometry are characterized by direct current and by S-parameter measurements up to 50 GHz. The HFET-based varactors show capacitance ratios up to 14 and cutoff frequencies up to 74 GHz. The MOSHFET-based devices, on the other hand, show lower capacitance ratios and poorer stability because of the insulation layer between electrodes and semiconductor     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS

This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps.     

Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

Chemical mechanical polishing of polymer films

Strategies to reduce capacitance effects associated with shrinking integrated circuit (IC) design rules include incorporating low resistivity metals and insulators with low dielectric values, or “low-κ” materials. Using such materials in current IC fabrication schemes necessitates the development of reliable chemical mechanical polishing (CMP) processes and process consumables tailored for them. Here we present results of CMP experiments performed on FLARE™ 2.0 using a specialized zirconium oxide (ZrO₂) polishing slurry. FLARE™ 2.0 is a poly(arylene) ether from AlliedSignal, Inc. with a nominal dielectric constant of 2.8. In addition, we provide insight into possible removal mechanisms during the CMP of organic polymers by examining the performance of numerous abrasive slurries. Although specific to a limited number of polymers, the authors suggest that the information presented in this paper is relevant to the CMP performance of many polymer dielectric materials.     

化学机械抛光中的颗粒技术

多层金属化是集成芯片以摩尔定律的速度更替的重要工艺手段.在多层金属化中,平坦的晶圆表面对每道工序的成功完成都是非常必要的,而化学机械抛光工艺能在每道工序之前将晶圆表面抛光.化学机械抛光主要是通过使用颗粒研浆去除材料来实现晶圆抛光.除了研浆本身的化学性质外,研浆的效果也受研磨颗粒性质的影响.如果我们能够更好的理解研磨颗粒...     

Evaluation of a copper metallization process and the electricalcharacteristics of copper-interconnected quarter-micron CMOS

Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10¹¹ atoms/cm² by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550°C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved     

三维闪存中基于钨互连的空气隙结构的制备工艺

将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。     

碱性抛光液对铜布线电特性的影响

随着互连电路的规模发展到亚微米级,互连延迟已经成为超过门延迟的重要因素。减小延迟在互连结构中是不可避免的问题。化学机械抛光是最适合在多层铜互连结构中达到平整化目的的手段。出于对整体过程的考虑,我们将考察化学机械抛光对铜晶圆片电特性的影响。在这篇文章中,我们将考察两种抛光液在化学机械抛光中的影响,一种抛光液是酸性抛光液,来自于SVTC,另一种是碱性抛光液,由河北工业大学提供的。着重考察了三个方面的特性,电阻,电容和漏电流。电阻测试结果显示,河北工业大学提供的抛光液抛光后,电阻更小。而被两种抛光液抛光后的电容则相差不多,电容值分别为1.2 E^-10F 和1.0 E^-10F。同样,河北工业大学提供的抛光液抛光后的漏电流是1.0E^-11A,低于SVTC提供的酸性抛光液。结果显示,河北工业大学提供的碱性抛光液会产生小的碟形坑和氧化物损失,优于SVTC提供的酸性抛光液。     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Characterization and modeling of oxide chemical-mechanicalpolishing using planarization length and pattern density concepts

Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. In the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length     

ULSI电路层间SiO_2介质CMP工艺与抛光液

阐明了化学机械抛光(CMP)工艺在集成电路制造中所发挥的关键作用,介绍了作为IC多层布线层间介质SiO2的化学机械抛光机理及其抛光液在化学机械抛光中扮演的重要角色,着重分析了影响SiO2介质化学机械抛光质量的主要因素并在此基础上提出CMP工艺的优化工艺条件以及今后SiO2介质CMP研究重点。     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

The heterogenous integration of GaN thin-filmmetal-semiconductor-metal photodetectors onto silicon

The heterogeneous integration of GaN thin-film metal-semiconductor-metal (MSM) photodetectors onto a host substrate of SiO₂-Si is reported. Thin-film GaN photodetectors were separated from the lithium gallate (LiGaO₂) growth substrate using selective etching, and contact bonded onto a SiO₂-Si host substrate. The thin-film MSMs exhibited a dark current of 13.36 pA and an UV photoresponse at 308 nm of 0.11 A/W at a reverse bias voltage of 20 V. This first demonstration of GaN thin-film device integration onto SiO₂-Si using a low-temperature integration process, combined with the advances in GaN material quality on LiGaO₂ substrates, enables the integration of GaN devices with Si circuitry for heterogeneously integrated systems     

GLSI多层布线钨插塞CMP表面质量的影响因素分析

随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对IC工艺中的全局平坦化提出了更高的要求。在特大规模集成电路(GLSI)多层布线化学机械抛光(CMP)过程中,抛光质量对器件的性能有明显影响。研究了多层互连钨插塞材料CMP过程中表面质量的影响因素及控制技术,分析了抛光过程中影响抛光质量的主要因素,确定了获得较高去除速率和较低表面粗糙度的抛光液配比及抛光工艺参数。