An interactive micro-computer implementation of craft with multiple objectives and side constraints

The interactive program, MOCRAFT, differs from other micro-computer versions of CRAFT in several respects. Unlike some versions which are written in BASIC and are slow to execute, or have limited size, or lack the features of the original, MOCRAFT is a full implementation of the SHARE Library FORTRAN code.

MOCRAFT also contains many features not found in any other versions of the well known and powerful facilities layout program, CRAFT (for Computerized Relative Allocation of Facilities Technique by Armour and Buffa). For example, MOCRAFT can utilize both cost-flow and REL data at the sme times, and is therefore a true multiple objective method. It can also accomodate constraints between arbitraty points and departments in the layout.

Originally developed at the University of Wisconsin-Milwaukee for control panel layouts, the source code for MOCRAFT has been extensively edited and enhanced at Cleveland State University. The code was originally implemented on CSU's VAX network by the author in 1985 and the first PC version was compiled by D'Souze and Mohanty, in 1987. This version of MOCRAFT, by the author, is an improvement over the first PC version, and runs on a standard configured IBM PC, XT or AT, with at least 256K bytes of RAM.     

Mesh layouts for block-based caches

Current computer architectures employ caching to improve the performance of a wide variety of applications. One of the main characteristics of such cache schemes is the use of block fetching whenever an uncached data element is accessed. To maximize the benefit of the block fetching mechanism, we present novel cache-aware and cache-oblivious layouts of surface and volume meshes that improve the performance of interactive visualization and geometric processing algorithms. Based on a general I/O model, we derive new cache-aware and cache-oblivious metrics that have high correlations with the number of cache misses when accessing a mesh. In addition to guiding the layout process, our metrics can be used to quantify the quality of a layout, e.g. for comparing different layouts of the same mesh and for determining whether a given layout is amenable to significant improvement. We show that layouts of unstructured meshes optimized for our metrics result in improvements over conventional layouts in the performance of visualization applications such as isosurface extraction and view-dependent rendering. Moreover, we improve upon recent cache-oblivious mesh layouts in terms of performance, applicability, and accuracy.     

Tiling, block data layout, and memory hierarchy performance

Recently, several experimental studies have been conducted on block data layout in conjunction with tiling as a data transformation technique to improve cache performance. In this paper, we analyze cache and translation look-aside buffer (TLB) performance of such alternate layouts (including block data layout and Morton layout) when used in conjunction with tiling. We derive a tight lower bound on TLB performance for standard matrix access patterns, and show that block data layout and Morton layout achieve this bound. To improve cache performance, block data layout is used in concert with tiling. Based on the cache and TLB performance analysis, we propose a data block size selection algorithm that finds a tight range for optimal block size. To validate our analysis, we conducted simulations and experiments using tiled matrix multiplication, LU decomposition, and Cholesky factorization. For matrix multiplication, simulation results using UltraSparc II parameters show that tiling and block data layout with a block size given by our block size selection algorithm, reduces up to 93 percent of TLB misses compared with other techniques. The total miss cost is reduced considerably. Experiments on several platforms show that tiling with block data layout achieves up to 50 percent performance improvement over other techniques that use conventional layouts. Morton layout is also analyzed and compared with block data layout. Experimental results show that matrix multiplication using block data layout is up to 15 percent faster than that using Morton data layout.     

A linear algebra framework for automatic determination of optimaldata layouts

This paper presents a data layout optimization technique for sequential and parallel programs based on the theory of hyperplanes from linear algebra. Given a program, our framework automatically determines suitable memory layouts that can be expressed by hyperplanes for each array that is referenced. We discuss the cases where data transformations are preferable to loop transformations and show that under certain conditions a loop nest can be optimized for perfect spatial locality by using data transformations. We argue that data transformations can also optimize spatial locality for some arrays without distorting temporal/spatial locality exhibited by others. We divide the problem of optimizing data layout into two independent subproblems: 1) determining optimal static data layouts, and 2) determining data transformation matrices to implement the optimal layouts. By postponing the determination of the transformation matrix to the last stage, our method can be adapted to compilers with different default layouts. We then present an algorithm that considers optimizing parallelism and spatial locality simultaneously. Our results on eight programs on two distributed shared-memory multiprocessors, the Convex Exemplar SPP-2000 and the SGI Origin 2000, show that the layout optimizations are effective in optimizing spatial locality and parallelism     

Quasidynamic layout optimizations for improving data locality

Compiler-directed locality optimization techniques are effective in reducing the number of cycles spent in off-chip memory accesses. Recently, methods have been developed that transform memory layouts of data structures at compile-time to improve spatial locality of nested loops beyond current control-centric (loop nest-based) optimizations. Most of these data-centric transformations use a single static (program-wide) memory layout for each array. A disadvantage of these static layout-based locality enhancement strategies is that they might fail to optimize codes that manipulate arrays, which demand different layouts in different parts of the code. We introduce a new approach, which extends current static layout optimization techniques by associating different memory layouts with the same array in different parts of the code. We call this strategy "quasidynamic layout optimization." In this strategy, the compiler determines memory layouts (for different parts of the code) at compile time, but layout conversions occur at runtime. We show that the possibility of dynamically changing memory layouts during the course of execution adds a new dimension to the data locality optimization problem. Our strategy employs a static layout optimizer module as a building block and, by repeatedly invoking it for different parts of the code, it checks whether runtime layout modifications bring additional benefits beyond static optimization. Our experiments indicate significant improvements in execution time over static layout-based locality enhancing techniques.     

On designing optimal parallel triangular solvers

This paper explores the problem of solving triangular linear systems on parallel distributed-memory machines. Working within the LogP model, tight asymptotic bounds for solving these systems using forward/backward substitution are presented. Specifically, lower bounds on execution time independent of the data layout, lower bounds for data layouts in which the number of data items per processor is bounded, and lower bounds for specific data layouts commonly used in designing parallel algorithms for this problem are presented in this paper. Furthermore, algorithms are provided which have running times within a constant factor of the lower bounds described. One interesting result is that the popular two-dimensional block matrix layout necessarily results in significantly longer running times than simpler one-dimensional schemes. Finally, a generalization of the lower bounds to banded triangular linear systems is presented.     

Game level layout from design specification

The design of video game environments, or levels, aims to control gameplay by steering the player through a sequence of designer‐controlled steps, while simultaneously providing a visually engaging experience. Traditionally these levels are painstakingly designed by hand, often from pre‐existing building blocks, or space templates. In this paper, we propose an algorithmic approach for automatically laying out game levels from user‐specified blocks. Our method allows designers to retain control of the gameplay flow via user‐specified level connectivity graphs, while relieving them from the tedious task of manually assembling the building blocks into a valid, plausible layout. Our method produces sequences of diverse layouts for the same input connectivity, allowing for repeated replay of a given level within a visually different, new environment. We support complex graph connectivities and various building block shapes, and are able to compute complex layouts in seconds. The two key components of our algorithm are the use of configuration spaces defining feasible relative positions of building blocks within a layout and a graph‐decomposition based layout strategy that leverages graph connectivity to speed up convergence and avoid local minima. Together these two tools quickly steer the solution toward feasible layouts. We demonstrate our method on a variety of real‐life inputs, and generate appealing layouts conforming to user specifications.     

VisualTPL: A visual dataflow language for report data transformation

Data transformation, an important part of report generation, converts the layout of source data into a new layout suitable for presentation. Many report tools have been developed for end-users to specify data transformation. However, current report tools only support a limited set of report layouts. This paper proposes a visual dataflow programming language, called VisualTPL, to resolve this problem. Data transformation is accomplished by writing graphical dataflow programs, which manipulate tables as first-class objects with a set of extendable table operations. A report tool, called VisualTPS, has been developed to offer an easy and intuitive end-user programming environment. Reports with sophisticated layouts can be created through top-down decomposition and incremental development. An evaluation has been conducted to assess end-users' performance with VisualTPL. The results indicated that end-users could learn VisualTPL in a short time and create complicated report layouts all by themselves. And, in comparison with a commercial report tool, VisualTPL offered end-users similar performances and was preferred over the commercial tool.     

A Comparison of User-Generated and Automatic Graph Layouts

The research presented in this paper compares user-generated and automatic graph layouts. Following the methods suggested by van Ham et al. (2008), a group of users generated graph layouts using both multi-touch interaction on a tabletop display and mouse interaction on a desktop computer. Users were asked to optimize their layout for aesthetics and analytical tasks with a social network. We discuss characteristics of the user-generated layouts and interaction methods employed by users in this process. We then report on a web-based study to compare these layouts with the output of popular automatic layout algorithms. Our results demonstrate that the best of the user-generated layouts performed as well as or better than the physics-based layout. Orthogonal and circular automatic layouts were found to be considerably less effective than either the physics-based layout or the best of the user-generated layouts. We highlight several attributes of the various layouts that led to high accuracy and improved task completion time, as well as aspects in which traditional automatic layout methods were unsuccessful for our tasks.     

Topology optimization of continuum structures with different tensile and compressive properties in bridge layout design

In order to solve elasticity problems with dual extension/compression modulus this paper presents a technique that employ Heaviside function to describe the nonlinear relationship of stress and material modulus smoothing the constitutive discontinuity. An initial stress technique is utilized in the FEM based numerical analysis, which may lead to a higher computing efficiency since the stiffness matrix needs to be triangularized only once in the whole computing, moreover, avoid the inconvenience induced by choosing shear modulus in the conventional iterative algorithm. Furthermore, a multimaterial model is proposed to formulate the topology optimization problem for bridge layout designs. Two types of materials which are concrete and steels are distributed within the design domain to accommodate design need. In addition, sensitivity of the new material model is derived using the adjoint method. The effectiveness of the present design methodology and optimization scheme is then demonstrated through numerical examples.     

A shape-based block layout approach to facility layout problems using hybrid genetic algorithm

In this paper, a shape-based block layout (SBL) approach for solving facility layout problem with unequal-areas and fixed-shapes is presented. The SBL approach employs hybrid genetic algorithm to find good solution. The existing algorithms for the problem of assigning positions to unequal-area and fixed or approximated shape departments within a given building area can produce solutions with some drawbacks, which require extensive manual revision to create practical layouts and produce irregular building shapes and too much unusable spaces. The objective function of SBL approach minimizes total material handling cost and maximizes space utilization. Experimental results show that the SBL approach is able to improve solution and it can create more practical layout than that of existing approaches.     

Banner layout retargeting with hierarchical reinforcement learning and variational autoencoder

In many advertising areas, banners are often generated with different display sizes, so designers have to make huge efforts to retarget their designs to each size. Automating such retargeting process can greatly save time for designers and let them put creativity on new ads. This paper proposes a hierarchical reinforcement learning-based (HRL-based) method and a variational autoencoder-based (VAE-based) method by treating the automated banner retargeting problem as a layout retargeting task. The HRL and VAE models are trained separately to learn the scaling and positioning policy of the design elements from an original (base) layout. Hence, the proposed method can generate appropriate layouts for different target banner sizes. Meanwhile, evaluation metrics are proposed to assess the quality of generated layouts and are also reward conditions during the training process. To evaluate performances of the two models, SOTA methods such as Non-linear Inverse Optimization (NIO), Triangle Interpolation (TI), and Layout GAN (LGAN) are implemented and compared. Experimental results show that both HRL- and VAE-based methods retarget design layouts effectively, and the VAE model achieves better performance than the HRL model.

     

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.     

LLAMA: The low-level abstraction for memory access

The performance gap between CPU and memory widens continuously. Choosing the best memory layout for each hardware architecture is increasingly important as more and more programs become memory bound. For portable codes that run across heterogeneous hardware architectures, the choice of the memory layout for data structures is ideally decoupled from the rest of a program. This can be accomplished via a zero-runtime-overhead abstraction layer, underneath which memory layouts can be freely exchanged. We present the low-level abstraction of memory access (LLAMA), a C++ library that provides such a data structure abstraction layer with example implementations for multidimensional arrays of nested, structured data. LLAMA provides fully C++ compliant methods for defining and switching custom memory layouts for user-defined data types. The library is extensible with third-party allocators. Providing two close-to-life examples, we show that the LLAMA-generated array of structs and struct of arrays layouts produce identical code with the same performance characteristics as manually written data structures. Integrations into the SPEC CPU^® lbm benchmark and the particle-in-cell simulation PIConGPU demonstrate LLAMA's abilities in real-world applications. LLAMA's layout-aware copy routines can significantly speed up transfer and reshuffling of data between layouts compared with naive element-wise copying. LLAMA provides a novel tool for the development of high-performance C++ applications in a heterogeneous environment.     

Alternative approaches to the design of four-burner stoves

The spatial arrangement of stove hotplates and associated controls and linkages has been of concern to ergonomists. In this study, two different approaches were used to determine preferred arrangements. In the first, one group of participants were given locations of controls and asked to place hotplates; a second group was given hotplate locations and asked to place controls. In each case, linkages were to be indicated. In the second approach, drawings of stove layouts with controls and linkages were given. Scales of preference of control/hotplate layouts were established. Arrangements having high spatial congruence between hotplate and controls were nominated and most preferred by participants in the first approach. In the second approach, it was found possible to discriminate between arrangements that had high spatial congruence and high compatibility between hotplate and control and, hence, to determine 'best' designs in terms of participant preferences. STATEMENT OF RELEVANCE: Most research on stove layout has been with hotplates in a square arrangement. Two different approaches to design show the importance of spatial congruence between hotplate and control for obtaining preferred designs having high compatibility, which are superior from an ergonomics viewpoint.     

Ovals for Any Given Proportion in Architecture: A Layout Possibly Known in the Sixteenth Century

Oval forms have been used in architecture since antiquity as arch elevations, cross and horizontal sections of vaults, profiles of arches and building plan layouts. The present paper aims to approach the knowledge and application of oval layouts for any given proportion, that is, those which fit a particular place, either as the span and height of an arch or vault, or as the length and width of a plan, by comparing written sources and built heritage. This is, on one hand, research on architectural treatises since the sixteenth century in order to find where the geometrical construction for this kind of layouts appears for the first time; and on the other, a study of the application of ovals in the vaults of the Escorial (1563-1584). Although 1712 could be considered the date of the first published geometrical construction for an oval to fit a given place, this work hypothesizes the possible application of a layout of this type in the construction of the Escorial.     

Adaptive document block segmentation and classification

This paper presents an adaptive block segmentation and classification technique for daily-received office documents having complex layout structures such as multiple columns and mixed-mode contents of text, graphics, and pictures. First, an improved two-step block segmentation algorithm is performed based on run-length smoothing for decomposing any document into single-mode blocks. Then, a rule-based block classification is used for classifying each block into the text, horizontal/vertical line, graphics, or-picture type. The document features and rules used are independent of character font and size and the scanning resolution. Experimental results show that our algorithms are capable of correctly segmenting and classifying different types of mixed-mode printed documents.     

虚拟角色骨骼模型建立方法研究

针对传统虚拟角色建模方法需要大量人力和时间的缺点,提出了一种虚拟角色骨骼模型自动生成方法.该方法通过对角色模型分块,再对各个块进行边界抽取,找到关节点,然后根据块的层次关系自动生成骨骼模型.最后探讨了应用骨骼平滑和边界缝合算法解决角色模型运动不自然的问题.     

Structure and spatial consistency of network-based space layouts for building and product design

Network-based space layouts are schematic models of whole spaces, subspaces, and related physical elements. They address diverse space modeling needs in building and product design. A schema (data model) for network-based space layouts is defined that is influenced by existing space schemas. Layout elements and selected spatial relations form a geometric network. The network is embedded in 3-space and facilitates analysis with graph and network algorithms. Spatial constraints on layout elements and spatial relations extend the schema to support spatial consistency checking. Spatially consistent layouts are required for reliable network analysis and desirable for layout modification operations. An operation is introduced that evaluates spatial constraints to detect and semi- or fully-automatically resolve spatial inconsistencies in a layout. A layout modeling system prototype that includes proof-of-concept implementations of the layout schema extended by spatial constraints and the inconsistency resolution operation is described. Layouts of a floor of an office building and a rack server cabinet have been modeled with the system prototype.     

Efficiency analysis for stochastic dynamic facility layout problem using meta-heuristic,data envelopment analysis and machine learning

The facility layout problem (FLP) is a combinatorial optimization problem. The performance of the layout design is significantly impacted by diverse, multiple factors. The use of algorithmic or procedural design methodology in ranking and identification of efficient layout is ineffective. In this context, this study proposes a three-stage methodology where data envelopment analysis (DEA) is augmented with unsupervised and supervised machine learning (ML). In stage 1, unsupervised ML is used for the clustering of the criteria in which the layouts need to be evaluated using homogeneity. Layouts are generated using simulated annealing, chaotic simulated annealing, and hybrid firefly algorithm/chaotic simulated annealing meta-heuristics. In stage 2, the nonparametric DEA approach is used to identify efficient and inefficient layouts. Finally, supervised ML utilizes the performance frontiers from DEA (efficiency scores) to generate a trained model for getting the unique rankings and predicted efficiency scores of layouts. The proposed methodology overcomes the limitations associated with large datasets that contain many inputs / outputs from the conventional DEA and improves the prediction accuracy of layouts. A Gaussian distribution product demand dataset for time period T = 5 and facility size N = 12 is used to prove the effectiveness of the methodology.