大数模幂乘算法的快速实现

大素数的选取是构造RSA密钥的关键 ,在素数的产生及测试是RSA公钥系统中的一个重要研究课题。描述了公钥密码体制中DSA、RSA等数据加密算法的原理及加密、解密过程 ,分析了各种算法的性能和适用的场合 ,针对上述算法的计算量巨大的问题 ,给出了实现数据加密较好的方法。理论和实验表明 ,该算法用于实现RSA算法 ,新算法的效率有明显的提高     

High-speed iterative array for binary multiplication

An iterative array for the multiplication of binary numbers and also the addition of either one or two other numbers is proposed, employing r.o.m.s. as lookup tables. The regularity of this array should make it attractive for l.s.i. fabrication.     

Concise cellular array for multiplication and division

This letter describes how the combination of one of the simplest arithmetic cells and a new control?arithmetic cell can be used to form a versatile array for multiplication and division which uses fewer cells, and fewer gates per cell, than existing comparable arrays.     

High speed 2×4 array of differential quantum well modulators

The 3-dB bandwidth of the modulators was measured to greater than 3 GHz, and the time response was measured to 200 ps. By using short mode-locked pulses, the 3-dB bandwidth of the devices used as differential detectors was measured to be greater than 4 GHz and the risetime to be ~100 ps     

双通道触发的嵌入式阵列信号高速采集技术

提出一种基于双通道触发的嵌入式阵列信号高速采集技术,并进行系统优化设计.首先分析了嵌入式阵列信号高速采集系统总体设计构架,进行阵列信号采集的干扰滤波与检测算法设计,基于VXI总线技术设计了具有双通道触发功能的嵌入式阵列信号高速采集系统,实现系统的软件开发和仿真平台构建.系统调试和仿真结果表明,该系统进行嵌入式阵列信号采集的功能组合性较完备,实时性好,可靠度较高,系统具有较高的实用价值.     

基于双通道触发的嵌入式阵列信号高速采集技术

嵌入式控制系统的VXI总线数据采集的核心技术在于对嵌入式阵列信号的采集,通过对阵列信号的高速采集提高控制系统的快速信号处理和分析能力。提出一种基于双通道触发的嵌入式阵列信号高速采集技术,并进行系统优化设计。首先分析了嵌入式阵列信号高速采集系统总体设计构架,进行阵列信号采集的干扰滤波与检测算法设计,基于VXI总线技术设计了具有双通道触发功能的嵌入式阵列信号高速采集系统,实现系统的软件开发和仿真平台构建。系统调试和仿真结果表明,该系统进行嵌入式阵列信号采集的功能组合性较完备,实时性好,可靠度较高,系统具有较高的实用价值。     

Fully iterative fast array for binary multiplication and addition

A fast combinational circuit is described which can be used both as a multiplier and as an adder, either separately or together, giving a parallel binary output. The structure, which is completely iterative in terms of both cell logic and cell-interconnection pattern, is advantageous in large-scale integration.     

High-speed and low-power feRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

A novel design method for nonvolatile ferroelectric random access memory (FeRAM) using a merged bitline (BL)/plateline (PL) array architecture with a twin bitline-driven scheme is proposed. This method is effective in improving the FeRAM performance and reduces the power consumption. A 128 Kbit FeRAM prototype applying the proposed circuitry is implemented. The chip size, access time and memory array power dissipation are reduced to about 87, 44 and 15.8%, respectively, in comparison with those of conventional FeRAM.     

Comment on the speed of binary multiplication using cellular arrays

A known recoding algorithm is considered and is shown to yield a speed improvement of approximately 33% for serial multiplication. However, in the case of cellular-array multipliers, such a recoding appears to offer no advantage; instead, it may even result in a speed penalty owing to the sequential nature of the recoding algorithm.     

快速热电探测器

本文介绍铌酸锂、钽酸锂快速热电探测器的器件设计和工艺,包括器件响应率的计算和测定,以及四种常用材料激光损伤阈值的比较;讨论了压电谐振的产生机理和消除办法。     

高速光调制器

文章分析了适用于40Gbit／s等高速光传输系统的MZ和EA调制器的性能特点、现状及技术发展动向。     

使用高速逻辑分析仪探测高速数字系统

在过去几十年中,数字设计人员一直依赖逻辑分析仪,作为系统检验的主要工具。近年来,时钟速率的加快,已经迫使设计人员考虑系统所有部分的信号完整性,包括测试能力。逻辑分析仪探头不再是任意连接到系统上就能够保证成功,而是必须考察探头位置、负荷及与传输线的邻近程度等因素。本文考察了在探测高速数字系统时设计人员遇到的部分常见问题,     

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted     

High speed opto-electronic neural network

The first opto-electronic neural network, employing InGaAs/InP based, multi-quantum well, surface modulator/detector arrays and operating at speeds above 10 Mbit/s is reported. The network uses a novel architecture that has a computer generated holographic weight matrix outside the modulator and detector layers.<>     

High speed GaAs integrated circuits

Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.     

高速并行Reed-Solomon编解码器

采用多路复用流水线的思想,设计基于FPGA仿真测试的RS编解码的改进IBM算法,使用Verilog硬件编程语言实现,进一步提高RS编解码器的运行速度及纠错能力,扩大应用范围.系统设计的时序仿真表明解码器8路复用后的数据率高达116.65 b/s,最大纠错能力为7字节/204字节,达到良好效果.