Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Design of a novel chip on glass package solution for CMOS image sensor device

This paper presents a chip-on-glass (COG) package solution for CMOS image sensors based on highly precise and reliable bumping and flip-chip bonding techniques. The package is fabricated using three core techniques, namely the damage-free image sensor bumping technique, the wafer form glass substrate patterned technique, and the damage-free flip-chip bonding technique. Since the proposed package concept is new, the effects of the package geometry and material properties on the package reliability are uncertain in the initial design stage. A three-dimensional nonlinear finite element model of the proposed CMOS image sensor package is created. In the simulations, the applied thermal load is cooled from 200 °C to ambient temperature (25 °C) to model the thermal deformation and warpage of the package during the practical ACF assembly cooling process. The design parameters influencing the reliability of the package, i.e. the material properties of the ACF, the thickness of the image chip and the thickness of the optical glass are investigated. Two control levels are specified for the chip, glass, and ACF factors and a 2³ factorial design is created to determine the appropriate combination of material properties and geometric size. It is found that the glass thickness and the ACF properties significantly affect the thermal deformation of the package, while the chip and glass factors, and the interaction between them, significantly affect the warpage. Regression models are developed to perform a series of surface response simulations. Using the developed statistical tests and regression models, suitable material selection criteria and geometric sizes can be specified to satisfy various reliability considerations in the initial design stage.     

Development of chip-on-flex using SBB flip-chip technology

A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced.So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate.SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling.SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.     

Rapid power cycling of flip-chip and CSP components on ceramic substrates

Power cycling has been done for flip-chip and CSP components solder joined onto ceramic substrates. Cycle periods as short as 1 min were applied in the experiments where the chip temperature varied between about 30°C in the power off-state and 100–150°C in the power on-state. Disconnections of the joints were found after 4000–17 000 power cycles. The flip-chip components joined onto low temperature cofired ceramic substrate showed slightly better reliability than the components joined onto alumina substrate. Most of the samples showed clear effects of deterioration of the joints seen as increasing chip temperature for power on-state. The experimental results are compared with calculations based on modified Coffin–Manson equation as well as with one-dimensional simulations.     

Thermal management of AlGaN-GaN HFETs on sapphire using flip-chip bonding with epoxy underfill

Self-heating imposes the major limitation on the output power of GaN-based HFETs on sapphire or SiC. SiC substrates allow for a simple device thermal management scheme; however, they are about a factor 20-100 higher in cost than sapphire. Sapphire substrates of diameters exceeding 4 in are easily available but the heat removal through the substrate is inefficient due to its low thermal conductivity. The authors demonstrate that the thermal impedance of GaN based HFETs over sapphire substrates can be significantly reduced by implementing flip-chip bonding with thermal conductive epoxy underfill. They also show that in sapphire-based flip-chip mounted devices the heat spread from the active region under the gate along the GaN buffer and the substrate is the key contributor to the overall thermal impedance.     

Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies

An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions.     

Study of package warp behavior for high-performance flip-chip BGA

To meet the future needs of high pin count and high performance, the LSI die and package size of flip-chip BGA (FC-BGA) devices have become larger. As a result, package warpage due to mismatch of the coefficients of thermal expansion among the construction materials has become a more serious problem for package reliability. In this paper, package warpage is successfully measured by a 3-D surface profile method in the temperature range from −55 to 230 °C. Furthermore, the package warpage of FC-BGA was investigated to clarify the effect of the thermomechanical properties of the underfill resin. Based on the results, we constructed a model of the mechanism of package warpage. This paper proposes an optimized underfill resin that can achieve low package warpage and a long fatigue life of the solder bump. The future trends in underfill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.     

Novel thermally reworkable underfill encapsulants for flip-chipapplications

The flip-chip technique of integrated circuit (IC) chip interconnection is the emerging technology for high performance, high input/output (I/O) IC devices. Due to the coefficient of thermal expansion mismatch between the silicon IC (CTE=2.5 ppm/°C) and the low cost organic substrate such as FR-4 printed wiring board (CTE=18-22 ppm/°C), the flip-chip solder joints experience high shear stresses during temperature cycling. Underfill encapsulant is used to couple the bilayer structure and is critical to the reliability of the flip-chip solder interconnects. Current underfill encapsulants are filled epoxy-based materials that are normally not reworkable after curing. This forms an obstacle to flip-chip on board (FCOB) technology development, where unknown bad dies (UBD) are still a concern. Approaches have been taken to develop the thermally reworkable underfill materials in order to address the nonreworkability problem of the commercial underfill encapsulants. These approaches include introduction of thermally cleavable blocks into epoxides and addition of additives to the epoxies. In the first approach, five diepoxides containing thermally cleavable blocks were synthesized and characterized. These diepoxides were mixed with hardener and catalyst. Then the mixture properties of Tg, onset decomposition temperature, storage modulus, CTE, and viscosity were studied and compared with those of the standard formulation based on the commercial epoxy resin ERL-4221E. These mixtures all decomposed at lower temperature than the standard formulation. Moreover, one mixture, Epoxy5, showed acceptable Tg, low viscosity, and fairly good adhesion. In the second approach, two additives were discovered that provide die removal capability to the epoxy formulation without interfering with the epoxy cure or properties of the cured epoxy system. Furthermore, the combination of the two approaches showed positive results     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Underfill of flip chip on organic substrate: viscosity, surface tension, and contact angle

In flip-chip packaging, an underfill is dispensed on one or two adjacent sides of the die. The underfill is driven by a capillary flow to fill the gap between the die and substrate. The application of an underfill reduces the stress to solder bumps and enhances the reliability of the solder joints. Underfill materials consist of epoxy or cyanate ester resins, catalyst, crosslinker, wetting agent, pigment, and fillers. Underfill materials are highly filled with the filler loading ranging from 40% to 70%. In terms of underfill material processing, fast flow and curing are desired for high throughput. The viscosity, surface tension, and contact angle are key material properties affecting the gap filling process. In order to achieve fast filling, it is required that an underfill material has low viscosity and low contact angle at dispensing temperatures. Due to curing of an underfill material at dispensing temperature, the viscosity increases with time, which complicates the underfill flow process. The rheological behavior of several underfill materials was experimentally studied. All the underfill materials showed strong temperature dependence in viscosity before the curing. The time dependent viscosity and curing of underfill materials were examined by a dynamic time sweep test. The effects of viscosity and curing behavior of underfill materials on underfill material processing were investigated. The material with a longer gel time had more stable viscosity at room temperature, and therefore longer pot life. Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C. Results showed that the contact angle for underfill on a substrate was time dependent. The interaction between underfill and substrate affects not only gap filling, but also filleting. The effect of surface energies of flip-chip substrates on wetting angles was also studied. Experiment results showed that for the same underfill, the higher the surface energy of substrate, the better the filleting.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

In process stress analysis of flip-chip assemblies during underfill cure

Low cost flip chip on board assemblies are analyzed during the underfill cure process to determine residual stress generation. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip-chip test vehicles, based on the Sandia National Laboratories’ ATC04 assembly test chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented with respect to the residual stresses produced by each underfill on the flip-chip assemblies. Significant stress variations are observed between the four underfills studied. Correlation between the glass transition temperature (T_g) and storage modulus (G^′) are made relative to residual stresses produced during underfill cure. Stress relaxation characteristics are also evaluated for the low cost flip-chip assemblies.     

Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.