高速3780点FFT处理器的设计与实现

介绍了地面数字电视多媒体广播传输系统(DTMB)中3 780点FFT处理器的设计与实现。通过综合利用混合基算法、素因子算法和WFTA算法,来完成3 780点FFT的算法设计。采用流水线结构进行硬件实现,为进一步提高系统吞吐率,其内部3,4,5,7,9点WFTA运算单元均采用并行数据处理方式。     

单精度浮点数FFT的FPGA实现

文中首先讨论了多种FFT算法及其基本原理,实现了基2频率抽取算法,采用单蝶形顺序处理的结构实现单精度浮点数FFT处理器。根据自顶向下的设计思想,将整个设计划分为6个子模块,分别对子模块进行设计,最后组合成FFT处理器。然后,文中介绍了浮点数加法器和浮点数乘法器的硬件实现,在其中引入流水线,大大提高了数据吞吐量,提高处理速度。在中间结果缓存单元的设计中,调用Altera IP Core中的三口RAM,能够同时读写数据,大大节省了运算时间。最后对FFT处理器进行了功能仿真和时序仿真,做了详尽的分析测试。结果表明,单精度浮点数FFT处理器达到了较高的运算精度,可稳定运行在62.5MHz,完成一次256点浮点数复数FFT运算需要33.056μs。与DSP和单片机实现的FFT相比,在性能上具有一定优势。     

基于FPGA的级联结构FFT处理器的优化设计

为了减少级联结构FFT处理器对缓冲存储器需求量,提出一种基于FPGA用基-16和基-2、基-4、基-8组合的混合基算法实现FFT处理器的设计方案。在1 024点FFT处理器的实现过程中,用优化的基-4蝶形运算核搭建了级联结构的基-16蝶形运算核,并将对同一个地址进行读和写的双端口RAM和乒乓结构的单端口RAM结合使用,从而在不增加逻辑单元使用和保证运算速度的情况下,大大减少了存储单元的使用量。     

高吞吐率双模浮点可重构FFT处理器设计实现

高吞吐浮点可灵活重构的快速傅里叶变换(FFT)处理器可满足尖端雷达实时成像和高精度科学计算等多种应用需求。与定点FFT相比,浮点运算复杂度更高,使得浮点型FFT的运算吞吐率与其实现面积、功耗之间的矛盾问题尤为突出。鉴于此,为降低运算复杂度,首先将大点数FFT分解成若干个小点数基2k 级联子级实现,提出分别针对128/256/512/1024/2048点FFT的优化混合基算法。同时,结合所提出同时支持单通道单精度和双通道半精度两种浮点模式的新型融合加减与点乘运算单元,首次提出一款高吞吐率双模浮点可变点FFT处理器结构,并在28 nm标准CMOS工艺下进行设计并实现。实验结果表明,单通道单精度和双通道半精度浮点两种模式下的运算吞吐率和输出平均信号量化噪声比分别为3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。归一化吞吐率面积比相比于现有其他浮点FFT实现可提高约12倍。     

高基FFT处理器高效地址产生算法

FFT算法是数字信号处理最常用算法,使用FFT处理器是进行FFT运算的重要手段之一。本文针对主基16局部流水的FFT处理器,提出了一种运用于高基FFT处理器的新型地址产生结构,能够进行16~4096点可变长的FFT运算,具有快速灵活的特点,且结构简单,适合FFT处理器中对数据通路控制的实现。     

非2-基FFT的素因子算法研究

提出一种新的非2-基N点FFT的素因子算法.该方案与原素因子分解算法比较,实现了各个小点数DFT的同址顺序运算,并通过简单的地址模加运算得到顺序的输出,省去了多余的整序运算,是一种通用N点FFT算法.设计结构规整简单,利于硬件实现.以中国数字电视广播地面传输标准(DTMB)规定的3 780点FFT为例,结合WFTA算法和混合基算法,介绍了算法的具体设计与实现方案.     

大点数FFT设计中提高资源利用率的方法

应用系统对于高速大点数快速傅里叶变换(FFT)处理器的需求越来越大,但大点数FFT意味着资源、面积和功耗的大幅提高,因此如何减少资源和芯片面积成为了在FFT设计中需要考虑的重要问题之一。介绍了适合于大点数FFT设计的基16蝶形算法,并基于此算法针对如何在设计中提高运算单元和存储单元利用率的问题进行了探讨,提出了相应的解决方法。在FFT电路设计中进行了功能验证和资源比较,证实了方法的可行性。     

少模光纤通信频域均衡中的大点数FFT设计

为了减小频域均衡系统电路实现的功耗和面积,满足长距离少模光纤通信对均衡器的要求,对关键环节快速傅里叶变换(FFT)电路的实现进行了研究,采用2维分解算法将大点数的FFT运算转换为小点数FFT处理器的设计,降低了硬件复杂度。设计了基于现场可编程门阵列的高速蝶形运算核,实现了16384点FFT的2维R22SDF结构,提高存储器的资源利用率,减少了复数乘法器的使用;进行了理论分析和实验验证,取得了不同时钟频率下的电路结构占用资源的数据。结果表明,FFT运算器的正确性得到验证,该FFT运算器能够适应少模光纤通信系统中优化频域均衡电路结构的要求,能够实现200MHz数据传输速度的频域均衡实时处理。     

DTMB接收机中3780点FFT处理器的设计

提出了一种适合于DTMB接收机使用的FFT处理器的设计方法.该处理器基于混合基算法,素因子分解法和WFTA算法,采用动态截位法来保证精度与减小功耗和面积.FPGA验证表明：在输入输出均为13位时,该处理器的信噪比达到了60.4dB,运行最高频率达到84.48MHz,满足了DTMB接收机对FFT处理器的精度要求和速度要求.     

超高速全并行快速傅里叶变换器

设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器,其避免了复杂的路由寻址以及数据访问冲突等问题,基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定,大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元,在达到全并行结构的高速度同时硬件复杂度相对较低;所有的硬件计算单元处于满载的条件,其硬件效率能达到100%。根据实际的实现结果,所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升,同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。     

低成本可调FFT处理器的超大规模集成电路设计

文章提出了一种以基-22／23为基础的流水线结构,用以实现低成本、超大规模集成电路（VLSI）的快速傅里叶变换（FFT）处理器设计。该处理器在减少普通复数乘法器级数的同时,通过单路延时反馈（SDF）存取方式,以最少的存储字来获得FFT结果。对于数据通路,我们采用了混合浮点的数据缩放方式,在保证信噪比的同时,降低了数据长...     

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-/spl mu/m BiCMOS technology. The core area of this chip is 6.8 mm/sup 2/. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.     

Fixed-point error analysis of radix-4 FFT

Radix-4 FFT requires less number of multiplications than radix-2 FFT of the same size, and for the same throughput, it requires less hardware. Hence, quite often, radix-4 structure is preferred to radix-2 structure. This paper evaluates the error performance of radix-4 FFT algorithms (the input quantization error and the coefficient inaccuracy is not considered). The analysis assumes fixed-point two's complement arithmetic, with rounding in the case of multiplication, and truncation in the case of scaling. The predicted results of output noise agree closely with the computer simulation results. The different schemes of scaling for preventing arithmetic overflow are compared from the noise-to-signal ratio point of view. In comparison with radix-2, the radix-4 FFT has got a marginally better error performance.     

混合基可重构FFT处理器的设计与实现

本文提出了一种新型混合基可重构FFT处理器,由支持基-2/3FFT的新型可重构蝶形单元和多路并行无冲突的存储器组成,实现了FFT过程中多路数据并行性和操作的连续性.本设计在TSMC28nm工艺下的最高频率为1.06GHz,同时在Xilinx的XC7V2000T FPGA芯片上搭建了混合基FFT处理器硬件测试系统.对混合基FFT处理器的FPGA硬件测试结果表明,本设计支持基-2、基-3和基-2/3混合模式FFT变换,且执行速度达到给定蝶乘器数量下的理论周期值,对单精度浮点数,混合基FFT处理器可提供10-5的结果精度.     

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.     

Fast radix-3/9 discrete Hartley transform

An efficient algorithm for computing radix-3/9 discrete Hartley transforms (DHTs) is presented. It is shown that the radix-3/9 fast Hartley transform (FHT) algorithm reduces the number of multiplications required by a radix-3 FHT algorithm for nearly 50%. For the computation of real-valued discrete Fourier transforms (DFTs) with sequence lengths that are powers of 3, it is shown that the radix-3/9 FHT algorithm reduces the number of multiplications by 16.2% over the fastest real-valued radix-3/9 fast Fourier transform (FFT) algorithm     

A new radix-2/8 FFT algorithm for length-q/spl times/2/sup m/ DFTs

In this paper, a new radix-2/8 fast Fourier transform (FFT) algorithm is proposed for computing the discrete Fourier transform of an arbitrary length N=q/spl times/2/sup m/, where q is an odd integer. It reduces substantially the operations such as data transfer, address generation, and twiddle factor evaluation or access to the lookup table, which contribute significantly to the execution time of FFT algorithms. It is shown that the arithmetic complexity (multiplications+additions) of the proposed algorithm is, in most cases, the same as that of the existing split-radix FFT algorithm. The basic idea behind the proposed algorithm is the use of a mixture of radix-2 and radix-8 index maps. The algorithm is expressed in a simple matrix form, thereby facilitating an easy implementation of the algorithm, and allowing for an extension to the multidimensional case. For the structural complexity, the important properties of the Cooley-Tukey approach such as the use of the butterfly scheme and in-place computation are preserved by the proposed algorithm.     

一个高效的嵌入式浮点FFT处理器的实现

FFT是数字信号处理中的一种非常重要的算法。本文构造了一个适于嵌入式应用的基16FFT处理器局部流水结构,同时设计实现了一个高效的基4蝶形运算模块。我们的研究应用了局部流水和反馈的思想,使基16FFT蝶形运算模块得以由两个基4/基2蝶形模块组成的反馈流水电路实现,在简化结构的同时提高了处理速度。基4蝶形模块中运算模块的利用率达到100％,而且比传统的基四蝶形模块节省60％以上的资源。     

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-2² and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm² and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.