一种能够提高驱动能力和ESD保护能力的亚微米CMOS输出晶体管的新设计方法

本文给出了一种新的输出驱动器的设计方法，利用这种方法可以有效地减少CMOS输出驱动器的面积、同时提高驱动能力和ESD可靠性，输出驱动器是由许多电路单元组成的，电路单元有正方形、六边形和八边形三种形状。利用这种新的设计风格制成的输出晶体管结构更加对称，在ESD过程中触发更一致。理论计算和实验证明，在非硅化物CMOS工艺中，在小的设计面积内，利用新的设计方法研制成的CMOS输出缓冲器的输出驱动能力更高，ESD保护能力更强，有许多电路单元组成的输出晶体管和传统的指状设计相比，栅电阻更低，漏电容更小。     

Branch effect reduction techniques

Branch effects are the biggest obstacle to gaining significant speedups when running general purpose code on instruction level parallel machines. The article presents a survey which compares current branch effect reduction techniques, offering hope for greater gains. We believe this survey is timely because research is bearing much fruit: speedups of 10 or more are being demonstrated in research simulations and may be realized in hardware within a few years. The hardware required for large scale exploitation is great, but the density of transistors per chip is increasing exponentially, with estimates of 50 to 100 million transistors per chip by the year 2000     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

显示器行输出管损坏的原因分析及设计改进

行输出管损坏是显示器的高发故障，分析了因电源电压过高或逆程电容容量下降引起行电压过高或因行推动功率不足引起行输出管严重发热等最终导致行输出管损坏的主要原因，指出了更换行输出管要注意的要点，并针对手致行输出管损坏的主要原因，提出了通过改进设计减少故障发生的方法，改进后的显示器行输出管的损坏率将大大降低。     

Heterogeneous graphene–CMOS ternary content addressable memory

Leveraging nanotechnology for computing opens up exciting new avenues for breakthroughs. For example, graphene is an emerging nanoscale material and is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper we propose a novel graphene nanoribbon tunneling ternary content addressable memory (GNTCAM) enabled by xGNR device, featuring heterogeneous integration with CMOS transistors and routing. Benchmarking with respect to 16nm CMOS TCAM (which uses two binary SRAMs to store ternary information) shows that GNTCAM is up to 1.82× denser, up to 9.42× more power-efficient during stand-by, and has up to 1.6× faster performance during match operation. Thus, GNTCAM has the potential to realize low-power high-density nanoscale TCAMs. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.     

Opportunistic Transient-Fault Detection

CMOS scaling continues to enable faster transistors and lower supply voltage, improving microprocessor performance and reducing per-transistor power. The downside of scaling is increased susceptibility to soft errors due to strikes by cosmic particles and radiation from packaging materials. The result is degraded reliability in future commodity microprocessors. The authors target better coverage while incurring minimal performance degradation by opportunistically using redundancy.     

Fuzzy neural‐based approaches for efficient RF/microwave transistor modeling

In today's RF and microwave circuits, there is an ever‐increasing demand for higher level of system integration that leads to massive computational tasks during simulation, optimization, and statistical analyses, requiring efficient modeling methods so that the whole process can be achieved reliably. Since active devices such as transistors are the core of modern RF/microwave systems, the way they are modeled in terms of accuracy and flexibility will critically influence the system design, and thus, the overall system performance. In this article, the authors present neural‐ and fuzzy neural‐based computer‐aided design techniques that can efficiently characterize and model RF/microwave transistors such as field‐effect transistors and heterojunction bipolar transistors. The proposed techniques based on multilayer perceptrons neural networks and c‐means clustering algorithms are demonstrated through examples. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Development of a viable 3D integrated circuit technology

Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.     

Carbon nanotubes and semiconductor nanowires for active‐matrix backplanes

Abstract— Carbon nanotubes and semiconductor nanowires are a new class of materials currently being studied within the context of molecular electronics. Because of their excellent characteristics, transistors based on carbon nanotubes and semiconductor nanowires could become the workhorse of the post‐CMOS era. Since carbon nanotubes as well as Si or Ge nanowires can be grown at low temperature, using similar CVD‐type processes and on non‐crystalline and non‐refractory substrates, they could (and will) certainly be used in the near future for the fabrication of thin‐film transistors and active‐matrix backplanes. However, the development of these nanomaterials is hampered by the general problems posed by their manipulation, placement, and in‐plane organization. The possible use of CNT random networks (that do not need to be organised) for the fabrication of thin‐film transistors will be reviewed. Then a new way of organizing semiconductor NWs in a thin‐film transistor, based on the use of lateral porous anodic alumina templates, will be presented.     

On the stability of finite difference schemes in transient semiconductor problems

Nonlinear instabilities of explicit and half-implicit Crank-Nicholson schemes are analyzed by perturbation techniques. The time step is found to be inversely proportional to μN, a criterion which is in good agreement with experience. Based on this result, an optimal choice between the fast half-implicit method and the fully implicit Newton method is possible, favoring the former for Gunn-diodes and Schottky-barrier field-effect transistors, and the latter for insulated-gate field-effect transistors and some bipolar transistor problems.     

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.     

Critical transistors nexus based circuit-level aging assessment and prediction

Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in Integrated Circuits (ICs) design for advanced process technology nodes. In this paper we introduce a novel method to assess and predict the circuit reliability at design time as well as at run-time. The main goal of our proposal is to allow for: (i) design time reliability optimization; (ii) fine tuning of the run-time reliability assessment infrastructure, and (iii) run-time aging assessment. To this end, we propose to select a minimum-size kernel of critical transistors and based on them to assess and predict an IC End-Of-Life (EOL) via two methods: (i) as the sum of the critical transistors end-of-life values, weighted by fixed topology-dependent coefficients, and (ii) by a Markovian framework applied to the critical transistors, which takes into account the joint effects of process, environmental, and temporal variations. The former model exploits the aging dependence on the circuit topology to enable fast run-time reliability assessment with minimum aging sensors requirements. By allowing the performance boundary to vary in time such that both remnant and nonremnant variations are encompassed, and imposing a Markovian evolution, the probabilistic model can be better fitted to various real conditions, thus enabling at design-time appropriate guardbands selection and effective aging mitigation/compensation techniques. The proposed framework has been validated for different stress conditions, under process variations and aging effects, for the ISCAS-85 c499 circuit, in PTM 45 nm technology. From the total of 1526 transistors, we obtained a kernel of 15 critical transistors, for which the set of topology dependent weights were derived. Our simulation results for 15 critical transistors kernel indicate a small approximation error (i.e., mean smaller than 15% and standard deviation smaller than 6%) for the considered circuit estimated end-of-life (EOL), when comparing to the end-of-life values obtained from Cadence simulation, which quantitatively confirm the accuracy of the IC lifetime evaluation. Moreover, as the number of critical transistors determines the area overhead, we also investigated the implications of reducing their number on the reliability assessment accuracy. When only 5 transistors are included into the critical set instead of 15, which results in a 66% area overhead reduction, the EOL estimation accuracy diminished with 18%. This indicates that area vs. accuracy trade-offs are possible, while maintaining the aging prediction accuracy within reasonable bounds.     

A flexible,organic QVGA display with gray‐scale capability

Abstract— A flexible 4.7‐in. QVGA active‐matrix display was demonstrated, containing 76,800 solution‐processed organic transistors. The combination of our plastic active‐matrix backplane with electrophoretic‐ink display material developed by E‐Ink resulted in a reflective low‐power display with paper‐like appearance. By using high‐performance organic transistors, it was possible to generate 2‐bit images on the display. The display can be bent to a radius below 2 cm.     

一种低成本的新型步进电机驱动器的研制

开发了以单片步进电机控制器L297为控制核心，采用由晶体三极管和功率MOS管组成的分立式的功率驱动电路，以及以单片电流型脉宽调制（PWM）控制器S19114A为核心的高频开关电源电路构成的通用新型两相混合式步进电机驱动器。分析研究了系统的总体结构以及其中关键电路的工作原理和实现。通过实际测试和使用．证明该系统具有宽范围单一电源输入的特性，通用性强、可靠性高，并且成本低廉，可广泛应用于小型机电一体化设备中。     

Flexible microelectronics: New application for thin‐film transistors in fingerprint sensors

Abstract— Thin‐film transistors (TFTs) are field‐effect transistors that can be used to create large‐scale‐integrated (LSI) circuits. The combination of high‐performance TFTs and transfer technology of the TFTs has the potential to foster the rise of a new flexible microelectronics industry. This paper discusses the current status of flexible microelectronics, using a TFT fingerprint sensor (FPS) as an example. Technology used in active‐matrix displays can easily be applied to the TFT FPS. TFT technology should not be confined to the display industry; its use should be expanded into the semiconductor industry. With the result presented in this paper, we declare a new era of flexible microelectronics open.     

Oxide engineering of ZnO thin‐film transistors for flexible electronics

Abstract— In this paper, we show that ZnO thin‐film transistors (TFTs) are potentially a higher performance alternative to organic and amorphous‐Si TFTs for macroelectronics on plastic substrates. Specifically, we fabricated nanocrystalline ZnO thin‐film transistors using low‐temperature processing, compatible with flexible electronics on plastic substrates. The ZnO semiconductor was rf magnetron sputtered, and the Al₂O₃ gate dielectric was deposited either by electron‐beam evaporation or atomic layer deposition. By controlling the partial pressure of oxygen pO₂) during ZnO sputtering, we could engineer the field‐effect mobility of ZnO transistors to be between 2 and 42 cm²/V‐sec, attractive for high‐performance electronic applications. We contend that pO₂ controls the oxygen‐vacancy content or stoichiometry of ZnO, and that allows control of transistor field‐effect mobility. Although most of the devices described here were fabricated on Si substrates, devices we made on a thin (50 μm thick) polyimide substrate had about equivalent performance, affirming the compatibility of our processes with plastic substrates. Finally, we show that properties of our nanocrystalline ZnO transistors can be explained by transport models that account for grain‐boundary trapping of mobile carriers.     

Integrated Injection Logic: A Bipolar LSI Technique

Integrated injection logic or merged transistor logic is a novel bipolar circuit design approach to achieve high-density large-scale integration. As the basic logic units it uses multicollector npn transistors which are powered from merged multicollector lateral pnp transistors. I²L can be fabricated with standard buried collector technology and is therefore compatible with conventional bipolar circuitry on the same chip. The feature of having special interface circuitry—digital and/or linear—on the same chip renders I²L a powerful LSI technique.     

The Changing Design Landscape

This sidebar explains that the burden of enabling Moore's law to continue is gradually moving from the process technologists to the designers. As technology moves from 65 nm to 22 nm, the number of transistors on a big chip will go from approximately 2 billion to 15 billion. Technology scaling and the manufacturing process come with higher variations in transistors both locally and globally on a chip. Moreover, the large number of components on a single chip will lead to reliability, aging, and defect limitations that could no longer be eliminated through margins or overdesign. They must be detected and compensated without affecting the performance goals of the chip. The research direction of the GSRC is aimed at solutions to these obstacles, for the continued advancement of system performance needs.     

High-performance MEMS shutter display with metal-oxide thin-film transistors and optimized MEMS element

Active matrix prestressed microelectromechanical shutter displays enable outstanding optical properties as well as robust operating performance. The microelectromechanical systems (MEMS) shutter elements have been optimized for higher light outcoupling efficiency with lower operation voltage and higher pixel density. The MEMS elements have been co-fabricated with self-aligned metal-oxide thin-film transistors (TFTs). Several optimizations were required to integrate MEMS process without hampering the performance of both elements. The optimized display process requires only seven photolithographic masks with ensuring proper compatibility between MEMS shutter and metal-oxide TFT process.     

Sub 10 nm conjugated polymer transistors for chemical sensing

Chemical sensing responses of polythiophene transistors were investigated with various channel lengths down to sub 10 nm. To eliminate undesirable spreading currents, a novel four-terminal geometry was employed which ensures that the sensor active area is truly nanoscale. For the same analyte–semiconductor combination, the nanoscale devices exhibited drastically different responses compared with larger scale devices. In general, the nanoscale transistors experienced an increase in drain current upon exposure to analytes such as 1-pentanol and vanillin, whereas the larger devices showed a decrease. The chemical sensing mechanisms in both microscale and nanoscale transistors are briefly discussed.