A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

Blue-Enhanced PIN Finger Photodiodes in a 0.35-$mu{hbox {m}}$ SiGe BiCMOS Technology

Finger photodiodes in PIN technology are introduced to enhance the responsivity for blue and ultraviolet light. A thick low doped epitaxial layer results in high responsivity and high bandwidth also for red and near-infrared light. Results of PIN finger photodiodes are compared to that of PIN photodiodes for 10- and 15-mum epitaxial intrinsic layer thickness. The cathode finger structure results in a high responsivity of 0.20 A/W (quantum efficiency 61%) for 410-nm light and a bandwidth of 1.25 GHz for 10- mum epi thickness at a reverse bias voltage of 3 V. The rise and fall times with an epitaxial layer thickness of 15 mum are below 1 ns for the wavelength range from 410 to 785 nm.     

$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$mu{hbox {m}}$ CMOS

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P₁) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.     

A Single-Chip UHF RFID Reader in 0.18 $mu{hbox {m}}$ CMOS Process

A single-chip UHF RFID reader that integrates all building blocks—including an RF transceiver, IQ data converters, and a digital baseband—is implemented in a 0.18 $mu{hbox {m}}$ CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag's response of $-$70 dBm in the presence of $-$5 dBm self-interferer while occupying 18.3 ${hbox {mm}}^{2}$.      

High-Power 1.06-$mu{hbox {m}}$ Near-Diffraction-Limited Planar Tapered Amplifier Injected With Seed Light Through a Fiber Biconical Microlens

We designed a 1.06-mum single-quantum-well (SQW) InGaAs/AlGaAs planar tapered amplifier that was injected with seed light of a fiber Bragg grating stabilized laser diode through a fiber biconical microlens. To increase the amplifier output, the microlens with approximately 3- and 11-mum radii on vertical and horizontal axes, respectively, provides high coupling efficiency between the laser diode and the amplifier. The microlens also controls propagation in the tapered gain area to suppress the filament formation. In addition, the small radii of the microlens reduce near-end reflection at the amplifier input to prevent parasitic laser oscillation of the amplifier. We demonstrated near-diffraction-limited output of 5.5 W with the beam quality factor M² of 1.5 by using a 3-mm-long amplifier having an optical confinement factor of 1.2%.     

A 22–29-GHz UWB Pulse-Radar Receiver Front-End in 0.18-$mu{hbox{m}}$ CMOS

The design of a CMOS 22–29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-$mu{hbox{m}}$ CMOS process, the RX front-end chip occupies a die area of 3 ${hbox{mm}}^{2}$. On-wafer measurements show a conversion gain of 35–38.1 dB, a noise figure of 5.5–7.4 dB, and an input return loss less than $-$14.5 dB in the 22–29-GHz automotive radar band. The phase noise of the constituent QVCO is $-$107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.      

Self-Consistent Analysis of Carrier Confinement and Output Power in 1.3-$mu{hbox {m}}$ InAs–GaAs Quantum-Dot VCSELs

A self-consistent model comprising rate equations and thermal conduction equation is used to analyze the influence of self-heating on the carrier occupation, quantum efficiency, and output power of 1.3- $mu{hbox {m}}$ InAs–GaAs quantum dot (QD) vertical-cavity surface-emitting lasers (VCSELs). The simulation results show that the poor hole confinement in QDs is due to the thin wetting layer, and increase in QD density and layer number can significantly improve the self-heating effect and quantum efficiency of the device. The output power of the QD VCSEL is mainly determined by the quantum efficiency. High output power can be achieved by the high number of QD layers and QD density. However, there exists an optimized number of QD layers ($sim$15) to achieve the highest output power.      

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

A 1-V 45-GHz Balanced Amplifier With 21.5-dB Gain Using 0.18-$mu{hbox {m}}$ CMOS Technology

A fully integrated balanced amplifier was realized in a standard 0.18-mum CMOS technology. From the measured-parameters, a gain up to 21.5 dB was achieved at 45.4 GHz under a supply voltage of only 1 V and a total power consumption of 89 mW. An effective technique, i.e., pi-type parallel resonance, was proposed to enhance the device and circuit frequency response. In addition, the semicoaxial line structure was used to reduce the signal loss and physical size of the Lange couplers in the amplifier. To the best of the authors' knowledge, the proposed balanced amplifier demonstrated the highest operation frequency and the lowest operation voltage among the published millimeter-wave amplifiers using a similar technology.     

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A 750-MHz 6-b Adaptive Floating-Gate Quantizer in 0.35-$mu{hbox {m}}$ CMOS

A 6-b 750-MS/s flash analog-to-digital converter (ADC) uses nonvolatile analog storage for reference levels and achieves a signal-to-noise-plus-distortion ratio (SNDR) and a spurious-free dynamic range of 37.2 and 48.6 dB, respectively. The architecture comprises an array of adaptive floating-gate comparators that enables storage and programming of reference levels, eliminating the need for resistive ladders. Reference levels may be programmed either manually by the user or autonomously during normal analog-to-digital conversion. Autonomous programming achieves histogram equalization by adjusting reference levels for finer resolution and greater sensitivity at frequently visited signal values. When programmed manually, the ADC achieves 34.3-dB SNDR at 750 MS/s for input frequencies up to 2.07$times$ Nyquist rate, with a differential full-scale input range of 1 V. We observe integral nonlinearity and differential nonlinearity of less than 0.27 least significant bit at the Nyquist rate. One-month continuous operation shows no signs of reference-level drift due to charge leakage and maintains a constant bit error rate of $2.93times 10^{-9}/hbox{sample}$.      

125-GHz Diode Frequency Doubler in 0.13-$mu{hbox {m}}$ CMOS

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits $sim$10-dB conversion loss as well as $-$1.5-dBm output power at 125 GHz. The input matching is better than $-$10$~$dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66$~$GHz. The doubler can generate signals up to 140 GHz.      

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

High-Performance Focal Plane Array Based on InAs–GaSb Superlattices With a 10-$mu{hbox {m}}$ Cutoff Wavelength

We report on the demonstration of a focal plane array based on Type-II InAs-GaSb superlattices grown on n-type GaSb substrate with a 50% cutoff wavelength at 10 mum. The surface leakage occurring after flip-chip bonding and underfill in the Type-II devices was suppressed using a double heterostructure design. The R₀A of diodes passivated with SiO₂ was 23 Omegamiddotcm² after underfill. A focal plane array hybridized to an Indigo readout integrated circuit demonstrated a noise equivalent temperature difference of 33 mK at 81 K, with an integration time of 0.23 ms.     

Temperature Effect on $Ku$-Band Current-Reused Common-Gate LNA in 0.13-$mu{hbox{m}}$ CMOS Technology

This paper presents the temperature effect on a Ku-band NMOS common-gate low-noise amplifier (CG-LNA). The temperature characteristics of an NMOS transistor and spiral inductors are obtained over the temperature range from 253 to 393 K. These results show that the optimal bias condition minimizes the transconductance and drain current temperature variations. Based on these results, a current-reused CG-LNA with good temperature performance is designed. At ambient temperatures, the CG-LNA has a measured power gain of 10.3 dB and a noise figure (NF) of 4.3 dB at 15.2 GHz, while consuming 4.5 mA from a 1.3-V power supply. When the temperature varies from 253 to 393 K, the CG-LNA has a power gain variation of 3 dB, NF variation of 2 dB , and dc power consumption variation of 11.9%. This paper is the first to report the temperature effect on Ku-band CG-LNAs.     

Numerical Modeling of Pulsed Raman Fiber Converters at 2 $mu{hbox {m}}$

Theoretical modeling of stimulated Raman scattering (SRS) in fibers is presented for the near-infrared band around 2 mum, where pump and Stokes wave have different absorption. This model takes into account amplified spontaneous emission (ASE), SRS towards Stokes and anti-Stokes waves, absorption of the Raman medium and Rayleigh backscattering in fibers. Depending on the fiber configuration, this model includes the cavity parameters of either external or internal mirrors at the fiber ends. Input parameters are, among others, temporal profiles of the pump radiation, absorption, and gain curve of the Raman medium. The model agrees well with experimental results obtained with a GeO₂ doped core fiber pumped by a pulsed and tunable Tm:silica fiber laser emitting around 2 mum.     

Effects of Lateral Diffusion on the Temperature Sensitivity of the Threshold Current for 1.3-$mu{hbox {m}}$ Double Quantum-Well GaInNAs–GaAs Lasers

We present an experimental and theoretical investigation of the temperature dependence of the threshold current for double quantum well GaInNAs-GaAs lasers in the temperature range 10 degC-110 degC. Pulsed measurements of the threshold current have been performed on broad and narrow ridge wave guide (RWG) lasers. The narrow RWG lasers exhibit high characteristic temperatures (T₀) of 200 K up to a critical temperature (T_c), above which T₀ is reduced by approximately a factor of 2. The T0-values for broad RWG lasers are significantly lower than those for the narrow RWG lasers, with characteristic temperatures on the order of 100 (60) K below (above) T_c. Numerical simulations, using a model that accounts for lateral diffusion effects, show good agreement with experimental data and reveal that a weakly temperature dependent lateral diffusion current dominates the threshold current for narrow RWG lasers.     

InGaAs/GaAs 0.98- $mu{hbox {m}}$ Low-Divergence Central-Lobe Semiconductor Lasers With $delta$ -Doped Resonant Tunneling Quantum Wells

In this paper, we describe a new structure design for producing low-threshold, high-efficiency, and high-brightness 0.98-$mu{hbox {m}}$ lasers. In this structure, we incorporated a self-discriminating weak optical confinement asymmetrical waveguide coupled to passive waveguides, and an active region based on three InGaAs quantum wells (QWs) coupled to Te n-type $delta$-doping. Optimized coupling between the $delta$-doping and the three QWs, together with waveguide optimization and doping profile optimization, yields $J_{rm th}=98 {hbox {A/cm}}^{2}$ per QW, ${T}_{0}=80;^{circ}hbox{C}$, and a far-field central lobe angle of $sim 10^{circ}$.