Ka波段对极鳍线混频器和检波器设计

This paper mainly discusses the analysis and design of a finline single-ended mixer and detector. In the circuit, for the purpose of eliminating high-order resonant modes and improving transition loss, metallic via holes are implemented along the mounting edge of the substrate embedded in the split-block of the WG-finline-microstrip transition. Meanwhile, a Ka band slow-wave and bandstop filter, which represents a reactive termination, is designed for the utilization of idle frequencies and operation frequencies energy. Full-wave analysis is carded out to optimize the input matching network of the mixer and the detector circuit using lumped elements to model the nonlinear diode. The exported S-matrix of the optimized circuit is used for conversion loss and voltage sensitivity analysis. The lowest measured conversion loss is 3.52 dB at 32.2 GHz; the conversion loss is flat and less than 5.68 dB in the frequency band of 29-34 GHz. The highest measured zero-bias voltage sensitivity is 1450 mV/mW at 38.6 GHz, and the sensitivity is better than 1000 mV/mW in the frequency band of 38-40 GHz.     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum ⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm² including pads.     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz.This chip is composed of a single ended-into differential-out active Balun,balanced FETs in push-push configuration,and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power,and the fundamental frequency suppression is typically -20 dBc up to 44 GHz.The MMIC works at...     

A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps<4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5×0.95 mm².     

应用于DRM/DAB系统的高转换增益及线性度优化的新结构混频器

This paper focuses on a new design of a down-conversion mixer for a low-IF wideband receiver.Based on the folded structure and differential multiple gated transistor(DMGTR) technique,a novel quadrature mixer with a high conversion gain,a moderate linearity,and a moderate NF is proposed.The mixer is designed and implemented in a 0.18-m CMOS process,and can operate in a frequency range from 150 kHz to 1.5 GHz.The circuit performance is confirmed by both simulation and measurement results.The measurement results exhibit a peak conversion gain of 13.35 dB,a high third order input referred intercept point of 14.85 dBm,and a moderate single side band noise figure of 10.67 dB.Moreover,the whole quadrature mixer core occupies a compact die area of 0.122 mm2.It consumes a current of 3.96 mA(excluding the output buffers) under a single supply voltage of 1.8 V.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

利用简单电阻偏置网络实现的高线性度电流驱动型无源混频器

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering

A CMOS wideband front-end IC is demonstrated in this paper.It consists of a low noise transconductance amplifier（LNTA） and a direct RF sampling mixer（DSM） with embedded programmable discrete-time filtering.The LNTA has the features of 0.5-6 GHz wideband,wideband input matching and low noise.The embedded filter following the DSM operates in discrete-time charge domain,filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency.The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz.It shows a conversion gain of 12.6 dB and IP_1dB of-7.5 dBm at 2.4 GHz.It occupies a chip area of 0.23 mm² and consumes 14 mA DC current.     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

A wide band up-conversion mixer for cable television tuner

An up-conversion mixer implemented in a 0.35μm SiGe BiCMOS technology for a double conversion cable TV tuner is described, The mixer converts the 100MHz to 1000MHz band to the Intermediate Frequency of 1GHz above. The mixer meets the linearity and noise figure requirements for a TV tuner. The noise figure （IF） of 19.2-17.5dB, ldB compression of 12.1dBm, and gain of-1-0.7dB in the 900MHz band are achieved at a supply voltage of 5V. The power consumption is 47mW.     

终端式MEMS微波功率传感器的设计与制作

A terminating type MEMS microwave power sensor based on the Seebeck effect and compatible with the GaAs MMIC process is presented. An electrothermal model is introduced to simulate the heat transfer behavior and temperature distribution. The sensor measured the microwave power from –20 to 20 dBm up to 20 GHz. The sensitivity of the sensor is 0.27 mV/mW at 20 GHz, and the input return loss is less than –26 dB over the entire experiment frequency range. In order to improve the sensitivity, four different types of coplanar waveguide （CPW） were designed and the sensitivity was significantly increased by about a factor of 2.     

Design of a 24–40 GHz balanced low noise amplifier using Lange couplers

A wide band （24–40 GHz） fully integrated balanced low noise amplifier （LNA） using Lange couplers was designed and fabricated with a 0.15 μm pseudomorphic HEMT （pHEMT） technology. A new method to design a low-loss and high-coupling Lange coupler for wide band application in microwave frequency was also presented. This Lange coupler has a minimum loss of 0.09 dB and a maximum loss of 0.2 dB over the bandwidth from 20 to 45 GHz. The measured results show that the realized four-stage balanced LNA using this Lange coupler exhibites a noise figure （NF） of less than 2.7 dB and the maximum gain of 30 dB; moreover, a noticeably improved reflection performance is achieved. The input VSWR and the output VSWR are respectively less than 1.45 and 1.35 dB across the 24–40 GHz frequency range.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

基于砷化镓工艺的集成式功分器

A compact lumped integrated power divider with low insertion loss using 0.5 μm GaAs pHEMT technology is presented. The proposed power divider uses the π-type LC network for transmission line equivalence and a thin film resistor for isolation tuning simultaneously. The quality factor of the inductor is analyzed and synthesized for insertion-loss influence. The measured insertion loss is less than 0.5 dB when the operating frequency is within the range of 5.15-6.15 GHz. The return loss and isolation are better than 15 dB and 20 dB, respectively. The compact dimension of the power divider is as small as 0.9 × 0.85 mm^2. The measured results agree well with the simulated ones.     

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size.     

A New Low Voltage RF CMOS Mixer Design

A new architecture of CMOS low voltage downconversion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is －4.5dBm,NF is 17dB,the maximum transient power dissipation is 9.3mW，and DC power dissipation is 9.2mW.The mixer’s noise and linearity analyses are also presented.