Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-mum CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP₃ of -8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 muW, respectively.     

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [forGPS receiver]

In recent years, much research has been carried out on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies, for radio-frequency (RF) applications. An example of such an application is the Global Positioning System (GPS). One of the important bottlenecks to make the transition to pure CMOS is the immunity of the circuits against electrostatic discharge (ESD). This paper shows that it is possible to design a low-noise amplifier (LNA) with very good RF performance and sufficient ESD immunity by carefully co-designing both the LNA and ESD protection. This is demonstrated with a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human body model (HBM) with a power consumption of 9 mW. The circuit was designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is implemented in a standard 0.25-μm 4M1P CMOS process     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

Development of microwave multilayer plastic-based multichip modules

We present the design and development of multilayer plastic-based multichip modules (MCM) at microwave frequencies. A vertical feed-through interconnect, which consists of embedded copper wires in plastic, has been developed to transport RF/microwave and dc signals from the first to the second packaging level. The development of this vertical feed-through enables plastic modules to be configured in a surface mount topology that can be interfaced with low cost FR-4 boards using ball grid arrays (BGA). The experimental analysis results demonstrate that this vertical feed-through used with BGAs has ultra-low parasitics and achieves a return loss of greater than 20-dB at 4-GHz. In addition, we demonstrate a number of packaged active microwave circuits including a switch, a low noise amplifier (LNA) and a power amplifier using the plastic module technology at microwave frequencies     

Design Considerations for High Performance RF Cores Based on Process Variation Study

RF circuits play a vital role in high data rate communication systems. Although at the design stage several considerations are made to ensure that the designed circuit functions as per desired specifications, the effect of process variations on the circuit’s performance is less understood. The parametric variations arising from the various stages of fabrication play a significant role in determining the device characteristics. In this paper, in order to analyze the effect of process variations, we consider a bottom–up approach beginning at the component level for active and passive elements and then move to the circuit level in an RF circuit consisting of both analog and digital components. We take Low Noise Amplifier (LNA) and a Phase Frequency Detector (PFD) which is one of the important building blocks of a Phase Locked Loop (PLL) as case studies for circuit level analysis. In the case of LNA, the performance is analyzed in terms of the S-parameters, gain and Noise Factor on different topologies and for a PFD, an analytical model is developed and the analysis is carried out using the Monte Carlo method to verify the robustness of the circuit elements towards phase noise. Our hierarchical multi-phase analysis technique is shown to provide valuable insights into designing robust RF circuits.     

Design of a 0.18μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier(LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage....     

Impact of intrinsic channel resistance on noise performance of CMOSLNA

Channel resistance cannot be neglected for CMOS circuits that operate at radio frequency (RF), especially for a low noise amplifier (LNA), which is a very important block in CMOS RF transceivers. The impact of channel resistance on the noise performance of an LNA is thoroughly studied and analyzed and new formulas are proposed systematically in this work. Furthermore, a revised noise figure optimization technique is discussed. Simulation results are also proposed. All of this work will be very instructive for the design of high-performance LNA     

双频段接收机中的BiFET低噪声放大器

设计了一种采用BiFET结构的低噪声放大器（LNA）,这种结构通过BiCMOS工艺使低噪声放大电路集合了双极型晶体管的低噪声特性和CMOS晶体管的高线性度。应用优化的BiFET Cascode共源共栅结构能够明显地提高低噪声放大器的性能,并且能应用于两个不同频率。本文设计的低噪声放大器在低偏置电流（1．7mA）和低功耗（5．7mW）的情况下能取得1．69dB的噪声系数、15．96dB的电压增益、一8．5dBm的IIP3和-67dB的反向隔离。设计的BiFET低噪声放大器是采用了AMS0．8μm的BiCMOS混合信号工艺,经过优化可以用于工业、室内的远程无线控制系统包括无线门禁系统。     

用于便携式GPS接收机中的5.4mW低噪声高增益CMOS射频前端电路设计

设计了应用于便携式GPS接收机射频前端中的CMOS低噪声放大器和正交混频器.该电路中的低噪声放大器采用带源端电感负反馈的输入级,并引入功耗约束下的噪声和输入同时匹配技术.正交混频器基于吉尔伯特单元.电路采用TSMC 0.18μm RFCMOS工艺实现,总的电压转换增益为35dB,级联噪声系数为2.4dB,输入ldB压缩点为-22dBm,输入匹配良好,输入回损为-22.3dB,在1.8V电压供电下,整个全差分电路功耗为5.4mW.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance

The intrinsic channel resistance, which is caused by the finite charging time of the carriers in the inversion layer, has remarkable impact on RF CMOS circuits, especially low noise amplifier (LNA), the first block of receiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed in this paper, and then new formulae are proposed systematically. Moreover, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier (LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

Input impedance matching optimization for adaptive low-power low-noise amplifiers

Portable and implantable devices with wireless connectivity generate a high demand for low-power RF circuits. Biasing transistors in the subthreshold region allows significant reduction of power consumption, but calls for effective design techniques to minimize performance tradeoffs. This paper addresses one of the challenges associated with subthreshold RF low-noise amplifier (LNA) design: The input impedance of the ubiquitous CMOS inductor-degenerated common-source LNA operated in the subthreshold region is analyzed. By taking the increased impact of larger parasitic capacitances in the subthreshold region into account, the proposed input impedance equations provide more precise S₁₁ prediction than the conventional approximation. In addition, a tuning method for the LNA’s input impedance is presented to guarantee matching in the presence of manufacturing process variations. This tuning is implemented with a programmable capacitance to allow for digitally-assisted calibration. A 2.4 GHz LNA was designed in 0.18 μm CMOS technology and post-layout simulations were performed with device corner models across temperature and supply voltages variations. With these variations and ±15 % source/gate inductor tolerance, the simulated S₁₁ (<?16 dB) of the tunable LNA is at least 8.5 dB better than for the identical reference design without tuning, while minimally affecting other performance parameters.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

一种基于接收机整机噪声最佳的射频LNA匹配电路设计

本文利用等增益圆、等噪声圆概念并结合计算机优化，提出了一种以射频接收机整机噪声系数最佳为目标的LNA匹配电路设计方法，给出了理论依据、设计方法和设计实例。该方法适用于利用现有商用芯片设计无线射频通信系统的场合。     

CMOS射频集成电路的研究进展

近年来，射频集成电路(RFIC)的应用和研究得到了飞速的发展，CMOS射频IC的研究更是成为该领域的研究重点和热点。文章对CMOS技术在射频和微波领域的应用进行了详细的探讨，着重介绍了当前射频通讯中常用的收发机结构及其存在的问题和解决方案；分析了射频收发机前端关键电路模块低噪声放大器(LNA)、混频器(Mixer)、压控振荡器(VCO)、功率放大器(PA)和射频关键无源元件的最新研究进展；展望了CMOS技术在射频领域的发展前景。