Core与总线系统的异步通信接口设计

文章基于GALS（Globally Asynchronous Locally Synchronous）设计理念，提出一个Core的异步接口设计模型：门控时钟停Core机制、握手机制、电平转脉冲逻辑等构成的异步控制信号处理模型：异步FIFO和双FIFO结构构成的异步数据处理模型。此结构允许Core和总线系统在完全异步的时钟域上工作。FPGA验证结果表明．该模型能正确地实现两者问的信号同步，并能满足具体应用的带宽需求。     

异步Viterbi解码器同步接口的设计

提出了一种利用异步 FIFO ( First In First Out)连接异步逻辑电路与同步逻辑电路的方法 ,并设计实现了相应的异步 FIFO电路 ,作为连接异步 viterbi解码器和其他同步逻辑电路的同步接口。对异步 FIFO的级数与异步 viterbi解码器内部的时序关系进行了分析。用逻辑仿真的动态时序分析表明 ,当同步电路时钟的周期大于 130 ns时 ,具有同步接口的异步 viterbi解码器可以与同步电路正常协同工作。具有简单接口电路的异步解码器 ,既能发挥异步电路功率效率高的优点 ,而且能嵌入同步电路系统     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 μm E/D MESFET process     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

异步FIFO在FPGA与DSP通信中的运用

利用异步FIFO实现FPGA与DSP进行数据通信的方案.FPGA在写时钟的控制下将数据写入FIFO,再与DSP进行握手后,DSP通过EMIFA接口将数据读入.文中给出了异步FIFO的实现代码和FPGA与DSP的硬件连接电路.经验证,利用异步FIFO的方法,在FPGA与DSP通信中的应用,具有传输速度快、稳定可靠、实现方...     

多FIFO灵活定制SDRAM控制器设计

针对SDRAM控制器设计复杂且可复用性低的特点,基于VerilogHDL提出了一种简单且可灵活定制异步FIFO的SDRAM控制器实现。图像预处理时经常会用到SDRAM来作为缓存,SDRAM的工作频率很高,所以一般会用异步FIFO缓存数据匹配它的频率,但是每次都重新设计FIFO的控制显然太繁琐。本设计结合FPGA的特点一方面简化SDRAM的控制时序提高了系统性能,另一方面在控制器中嵌入多路异步FIFO,当面对不同的设计需要时只需给设计关心的异步FIFO加载上数据、时钟、深度以及地址则可。既节约了逻辑资源又实现了重复使用的目的为后续设计节省了时间。     

一种新颖的低非线性全数字多相时钟产生电路

通过对传统的全数字多相位时钟产生电路进行分析和总结,提出一种新颖的延时校准算法。该算法通过优化调整延时单元的顺序,大大改善了全数字多相位时钟产生电路的非线性。整个电路基于全数字延迟锁相环,采用0.13μm CMOS工艺实现,并成功用于时间数字转换器中。输入时钟频率范围在110 MHz到140 MH间,对应的输出相位差为446 ps到568 ps,积分非线性小于0.35 LSB,微分非线性小于0.33 LSB。     

位填充导致USB数据传输紊乱的一种解决方案

通用串行总线(USB)数据传输中要对数据进行非归零翻转(NRZI)编解码、添加/去除位填充和串并/并串转换。添加/去除位填充使每字节数据传输所需的时间发生变化,再加上收发器与协议层的时钟频率不同,从而可能导致数据紊乱。以USB 2.0设备控制器中的收发器为例,在收发器与协议层间添加异步先入先出存储器(FIFO)作为缓存区可以解决这一问题。EDA软件仿真验证了该方法的可行性。     

高性能嵌入式UART IP核的设计

利用有限状态自动机理论[1]进行了可嵌入式UART的设计.支持AMBA 2.0 APB总线接口.采用了改进的异步FIFO,在提高传输速率的同时能够更加准确的判断出FIFO的空满状态.提出了一种新的小数分频的处理方法,操作简单,便于实现.设计通过了FPGA的仿真验证.嵌入到单板系统中,在UART时钟为12.5 M的情况下,实现了与ARM PSK系统中的UART以230 k以内的任意波特率的数据传输.试验结果证明了本设计的可行性.     

An on-chip frequency programmable test clock generation and application method for small delay defect detection

Small delay defects are posing a serious challenge to the quality and reliability of modern fabricated chips. A promising way for screening the timing-related defects in nanometer technology designs is faster-than-at-speed delay testing. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip frequency-programmable test clock generation method which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. With a reconfigurable launch-and-capture clock generator (LCCG) embedded on-chip, the required test clock, with a reconfigurable frequency and a high resolution, can be achieved by specifying the control information in the test patterns, which is then used to configure the LCCG. Similarly, the control information regarding test framework and clock signal selection can also be embedded in the test patterns. Experimental results are presented to validate the proposed method.     

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.     

USB3.0物理层中弹性缓冲的设计与实现

弹性缓冲用于在不同的时钟域中同步数据以保持数据的完整性,在USB、PCIE等高速串行总线的物理层中普遍应用.通过分析弹性缓冲的作用机制,根据USB3.O的协议要求,采用具有写指针屏蔽、指针跳跃、断点保存与握手、输出控制等具有创新功能的异步FIFO来设计弹性缓冲,很好实现了时钟频率补偿的目的.所设计的弹性缓冲采用并行10位数据,读写时钟可达到500 MHz的频率.该研究结论可用于满足USB3.0协议的弹性缓冲等高速弹性缓冲的场合,具有一定的工程应用价值.     

光传送网中复用映射电路的设计

为了简化光传送网中光数据单元的时钟电路设计、降低成本,提出了一种基于均匀缺口时钟的同步电路。首先,采用异步FIFO实现缺口同步时钟的生成;然后,通过带有缺口的同步时钟设计了一种复用映射电路,处理不同类型的光数据单元,实现信号频偏吸收、时钟数据恢复和前向错误纠错。并通过电路仿真证明,该方案设计的电路可达到与传统方案相同的性能,且设计和实现采用虚拟时钟替代锁相环,使电路更加简单经济。     

FPGA设计中的跨时钟域问题

随着FPGA设计中的时钟频率越来越高,时钟方案越来越复杂,跨时钟域问题变成了设计和验证中的关键点。为了解决跨时钟域问题对FPGA设计造成功能错误,对跨时钟域信号采用两级寄存器或多级寄存器同步、握手协议和异步FIFO等同步方法;同时还提出了不检查时序、修改SDF文件和添加约束文件三种仿真中的技术,解决了跨时钟域产生的亚稳态现象对FPGA仿真验证造成的影响。     

Multisim在触发器工作波形分析中的应用

介绍用Multisim仿真软件进行触发器工作波形仿真分析的方法,目的是探索触发器工作波形的仿真实验技术,即用Multisim仿真软件中的字组产生器产生触发器的时钟脉冲、数据输入、异步控制等多路信号,用Multisim中逻辑分析仪多踪同步显示触发器的各种输入及状态输出波形。并介绍了几种典型触发方式,不同逻辑功能触发器工作波形仿真分析时Multisim中字组产生器的设置方法。该软件可直观形象地描述触发器的逻辑功能和状态变化特点。所述方法的创新点是解决了触发器工作波形无法用电子实验仪器进行分析验证的问题。     

基于SoC低功耗MMC卡控制器的设计

本文基于最新的MMC4.1协议,设计了一款基于AHB总线的低功耗MMC卡控制器.设计采用了高性能改进异步FIFO.针对MMC卡常用于便携式产品中的低功耗需求,采用了动态功耗管理和门控时钟技术,可降低功耗约60%;探讨了一种基于SoC高性能接口控制器电路通用体系架构,已成功应用到多种接口控制器的设计中.设计通过了仿真(NC-Verilog)、综合(DC)以及FPGA验证,嵌入到单板系统中,实现了与MMC存储卡之间的数据传输.     

MIMO satellite communication with accelerated dual paths asynchronous design

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.     

带自测功能的DDR2控制器设计

在研究了JEDEC制定的DDR2标准的基础上,基于对DDR2快速测试的目的,设计了一种带自测功能的新型DDR2控制器。该控制器既拥有常见的控制时序、刷新、初始化等功能,又可以在没有外部激励的情况下对DDR2进行测试。整个设计完全遵循JEDEC标准,采用自顶向下的设计方法,通过异步FIFO进行跨时钟域的信号通讯,接口部分兼容FPGA的MCB模块,可以实现和MCB的简单替代,最后用verilog语言进行描述并通过仿真验证和FPGA验证．达到了较高的性能和实现了要求的功能。与常见的控制器相比,本设计虽然增加了自测试功能,但综合后的面积只增加10％。