椭圆曲线点乘算法的软硬件协同设计研究

椭圆曲线密码体制是一种基于代数曲线的公开密码体制,其中曲线的点乘速度决定了该密码体制的速度。以NiosII为核心的SOPC技术的发展代表了半导体和嵌入式系统的发展方向。文章在NiosII处理器上对椭圆曲线点乘算法给予了实现,并给出与8051单片机环境实现的速度比较分析,最后使用软硬件协同设计的方式进一步提高椭圆曲线点乘速度。     

基于分治算法的ECC乘法器结构及实现

针对椭圆曲线密码体制中的有限域乘法运算,讨论基本的串行结构、并行结构以及串并混合结构乘法器的硬件实现及存在的缺陷,提出一种改进的乘法器结构。该结构利用分治算法,通过低位宽乘法运算级联,降低运算复杂度,减少所需的时钟数。FPGA实验结果证明新结构在相同频率下有更小的面积和时间乘积。GF（2^233）域上椭圆曲线点乘采用此结构一次计算仅需0．811ms,满足椭圆曲线密码体制的应用要求。     

基于FPGA椭圆曲线密码体制的研究

对基于FPGA椭圆曲线密码体制的实现进行全面研究,在Xilinx的FPGA上实现了二元有限域和椭圆曲线点运算的所有算法。将模乘算法、模逆算法、曲线点加算法、曲线点减算法、点乘算法、EC-Elgamal加密／解密方案、总线命令控制等在FPGA上完成仿真、综合和板级验证,并设计出具有PCI局部总线传输功能的加密／解密适配卡。研究中提出了新的基于正规基和正则基的比特串行模乘算法实现方案。     

基于FPGA椭圆曲线密码体制的研究

对基于FPGA椭圆曲线密码体制的实现进行全面研究,在Xilinx的FPGA上实现了二元有限域和椭圆曲线点运算的所有算法。将模乘算法、模逆算法、曲线点加算法、曲线点减算法、点乘算法、ECElgamal加密/解密方案、总线命令控制等在FPGA上完成仿真、综合和板级验证,并设计出具有PCI局部总线传输功能的加密/解密适配卡。研究中提出了新的基于正规基和正则基的比特串行模乘算法实现方案。     

OCTEON处理器上实现国密SM2算法整体优化方案研究

SM2椭圆曲线公钥密码算法的核心运算是椭圆曲线上点乘算法,因此高效实现SM2算法的关键在于优化点乘算法。对椭圆曲线的点乘算法提出从底层到高层逐层优化的整体方案。上层算法使用带预计算的modified-w NAF算法计算点乘,中间层使用a=-3的Jacobian投影坐标系计算点加和倍点,底层基于OCTEON平台的大数乘加指令使用汇编程序实现模乘算法。最终在OCTEON CN6645处理器上实现该算法,实验结果表明:SM2数字签名速度提高了约540%,验证提高了约72%,加密提高了169%,解密提高了61%。     

Ⅱ类正规基快速模乘算法的设计与实现*

为寻求椭圆曲线密码应用系统中有限域上快速模乘算法,在Ⅱ类最佳正规基及其变形的类标准基基础上,提出了一种新的Ⅱ类最佳正规基快速模乘算法,并给出该算法FPGA实现的硬件结构。新的乘法器采用比特串行方式,使得硬件结构更加规则,减少了原有乘法器关键路径的延迟。试验数据表明,使用新的乘法器可以使整个椭圆曲线密码系统芯片工作频率大幅度提高。     

Ⅱ类正规基快速模乘算法的设计与实现

为寻求椭圆曲线密码应用系统中有限域上快速模乘算法，在Ⅱ类最佳正规基及其变形的类标准基基础上，提出了一种新的Ⅱ类最佳正规基快速模乘算法，并给出该算法FPGA实现的硬件结构。新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。试验数据表明，使用新的乘法器可以使整个椭圆曲线密码系统芯片工作频率大幅度提高。     

基于ECC的身份认证系统的设计与实现

本文从应用系统的安全性和高效性的要求出发,阐述了椭圆曲线密码体制的基本原理及其优点,设计了一个基于大素数域Fp椭圆曲线的身份认证系统,并对该系统进行了安全性分析。在椭圆曲线加密模块的实现中,大素数域中的模逆运算和椭圆曲线上的点乘运算经常是算法实现的瓶颈,本文采用模逆运算和点乘运算的改进算法来提高程序的运行效率。     

线性规划在椭圆曲线密码系统中的应用

提高椭圆曲线上点加运算的速度在整个基于FPGA设计的椭圆曲线密码应用系统实现中极为关键。在对已有的几种投影坐标系下的点加运算进行分析比较的基础上,提出了一种适合于FPGA设计实现的椭圆曲线上的点加运算方案。同时结合椭圆曲线密码系统具体约束给出了整数线性规划算法,并将该算法应用干曲线点加算法的并行优化处理。试验结果表明,优化后的投影坐标下的点加运算较原来的算法在速度上提高了22％。     

基于整数拆分的椭圆曲线密码体制上的快速点乘算法

在椭圆曲线密码系统中,其核心操作是点乘运算κP,P是椭圆曲线上的点,忌是整数。怎样提高点乘计算速度,已成为热点研究领域。本文提出了一种新的基于整数拆分与预计算相结合的快速点乘算法。     

RSA密码系统有效实现算法

本文提出了实现RSA算法的一种快速、适合于硬件实现的方案，在该方案中，我们作用加法链将求幂运算转化为求平方和乘法运算并大大降低了运算的次数，使用Montgomery算法将模N乘法转化为模R（基数）的算法，模R乘积的转化，以及使用一种新的数母加法器作为运算部件的基础。     

A floating point multiplier performing IEEE rounding and addition in parallel

In the conventional floating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it may accompany additional execution time and hardware components for renormalization which may occur by an overflow from the rounding operation. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by optimizing the operational flow based on the characteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this research. The floating point multiplier proposed does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.     

Applying systolic multiplication–inversion architectures based on modified extended Euclidean algorithm for GF(2) in elliptic curve cryptography

Elliptic curve cryptography is a very promising cryptographic method offering the same security level as traditional public key cryptosystems (RSA, El Gamal) but with considerably smaller key lengths. However, the computational complexity and hardware resources of an elliptic curve cryptosystem are very high and depend on the efficient design of EC point operations and especially point multiplication. Those operations, using the elliptic curve group law, can be analyzed in operations of the underlined GF(2^k) Field. Three basic GF(2^k) Field operations exist, addition–subtraction, multiplication and inversion–division. In this paper, we propose an optimized inversion algorithm that can be applied very well in hardware avoiding well known inversion problems. Additionally, we propose a modified version of this algorithm that apart from inversion can perform multiplication using the architectural structure of inversion. We design two architectures that use those algorithms, a two-dimensional multiplication/inversion systolic architecture and an one-dimensional multiplication/inversion systolic architecture. Based on either one of those proposed architectures a GF(2^k) arithmetic unit is also designed and used in a EC arithmetic unit that can perform all EC point operations required for EC cryptography. The EC arithmetic unit’s design methodology is proposed and analyzed and the effects of utilizing the one or two-dimensional multiplication/inversion systolic architecture are considered. The performance of the system in all its design steps is analyzed and comparisons are made with other known designs. We manage to design a GF(2^k) arithmetic unit that has the space and time complexity of an inverter but can perform all GF(2^k) operations and we show that this architecture can apply very well to an EC arithmetic unit required in elliptic curve cryptography.     

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log₂ N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N² – point by using synchronous clock tree.     

基于C8051F120的PI控制过程的快速运算

在控制系统的校正过程中,使用了增量式PI算法。在分析系统过程后,考虑到在PI校正中运算量集中在浮点数的乘法,运算速度有提升空间。为了提高校正程序运算速度,设计一种基于增量式PI算法的浮点数运算程序,将浮点数运算转化为整数乘法和移位,利用C8051 F120中的MACO(乘法和累加引擎),实现整数乘法和移位的快速运行。分析算法速度,运算时间缩短到原时间的27%。根据系统实际情况,分析数据运算精度,控制增量误差小于1%,能够保证系统控制精度,并得到实验验证。快速运算方法能够满足控制要求,硬件成本低,缩短了单周期内系统运算时间。     

基于改进4-2压缩结构的32位浮点乘法器设计

本文介绍一种用于高性能DSP的32位浮点乘法器设计,通过采用改进Booth编码的树状4-2压缩器结构,提高了速度,降低了功耗,该乘法器结构规则且适合于VLSI实现,单个周期内完成一次24位整数乘或者32位浮点乘。整个设计采用Verilog HDL语言结构级描述,用0.25um单元库进行逻辑综合.完成一次乘法运算时间为24.30ns.     

基于二值化密集卷积神经网络的表情识别算法

人脸表情识别已成为人工智能领域的重要研究课题,但传统的卷积神经网络需要庞大的计算资源使得其应用受限,而二值化卷积神经网络可通过快速与或运算代替原本的浮点乘法运算,大大降低了算法对计算资源的需求。论文提出了一种基于数据增强和二值化卷积神经网络的人脸表情识别算法,通过均值估计,在FER2013数据集上达到了66.15%的识别率,超越了部分基于浮点乘积运算的卷积网络,为表情识别算法移植到小型设备中提供了可能。     

OFDM系统中IFFT/FFT处理器的设计与实现

提出了Radix-4 FFT的优化算法,采用该优化算法设计了64点流水线IFFT/FFT处理器,该处理器可以在64个时钟周期内仅采用3个复数乘法器获得64点处理结果,提高了运算速度,节约了硬件资源。通过Xilinx XC2S300E Spartan2E系列的xc2s300e器件进行下载验证,仿真结果与MATLAB计算结果误差小于0.5%,该处理器已经成功应用于某OFDM通信系统中。     

椭圆曲线密码体制上的一种快速算法

本文分析了已有的一些计算椭圆曲线上点乘运算的快速算法，定义了整数阶乘展开式，并提出一种新的基于阶乘展开式的计算椭圆曲线上点乘的快速算法。对于200位的大整数点乘，与二进制算法相比，本文算法的倍点数减少了11％，点加数也有较大的减少。     

GF（3^m）椭圆曲线群快速算术运算研究

详细研究了GF(3m)上椭圆曲线基本算术运算,给出并证明GF(3m)上超奇异和非超奇异椭圆曲线仿射坐标系下点加、倍点、3倍点和3k倍点计算公式.提出高效3k倍点递归算法,在逆乘率较高时,其效率要优于逐次3倍点算法.在此基础上,提出一种新的变长滑动窗口wrNAF标量乘算法,其在保证较少点加法运算优点的同时可有效降低3倍点的计算量.