Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.     

A methodology aimed at better integration of functional verification and RTL design

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Computer-aided design in civil engineering

The paper reviews the development and current status of computer-aided design (CAD) in structural-engineering, a branch of civil engineering. The Similarities to and differences from electrical engineering practice are emphasized. The presentation deals first with well-developed CAD application areas, namely those supporting analysis, component selection and the preparation of design documents, Problematic areas, still subject to intense research, in synthesis, optimization, the representation of design specifications, the use of databases and the role of software engineering tools are briefly described.     

Hierarchical design methodologies and tools for VLSI chips

Hierarchical design methods are considered to be a means of managing the VLSI design problem. This paper will consider why this problem exists and discuss alternative means that can be used to arrive at a solution. The merits of design methodologies, with emphasis on hierarchical techniques, will be compared with those of automated design approaches. The discussion of hierarchy will lead to the conclusion that the method requires formal abstraction facilities in order to be effective. Hierarchical design methods permit the creation of a new generation of CAD programs that can both give a designer better support and can be much more efficient than the present generation of tools. An example of such a tool, VOILA, will be given.     

A methodology and design tools to support system-level VLSI design

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology     

A recursive design methodology for VLSI: Theory and example

A novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT²) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance.     

The applicability of computer-aided design as a system engineering tool

The morphology of design and the process of design are examined in an effort to establish a commonality between component and system design which would permit the expansion of design automation. The characteristics of a design problem that make it amenable to computer-aided design (CAD) are defined. The capabilities of CAD for the solution of these problems are analyzed and the difficulties facing the implementer outlined. It is concluded that a methodology for CAD development is essential to its use as a system engineering tool and that among the other needs are: commonality of programs, transferability of programs, better efficiency, and standardization of tools and techniques.     

Relating statistical MOSFET model parameter variabilities to ICmanufacturing process fluctuations enabling realistic worst case design

The implementation of a viable statistical circuit design methodology requiring detailed knowledge of the variabilities of, and correlations among, the circuit simulator model parameters utilized by designers, and the determination of the important relationships between these CAD model parameter variabilities and the process variabilities causing them is presented. This work addresses the above requirements by detailing a new framework which was adopted for a 2-μm CMOS technology to enable realistic statistical circuit performance prediction prior to manufacture. Issues relating to MOSFET modeling, the derivation of fast “direct” parameter extraction methodologies suitable for rapid parameter generation, the employment of multivariate statistical techniques to analyze statistical parametric data, and the linking of the CAD model parameter variations to variabilities in process quantities are discussed. In this approach the correlated set of model parameters is reduced to a smaller and more manageable set of uncorrelated process-related factors. The ensuing construction and validation of realistic statistical circuit performance procedures is also discussed. Comparisons between measured and simulated variabilities of device characteristics is utilized to demonstrate the accuracy of the techniques described. The advantages of the proposed approach over more traditional “worst case” design methodologies are demonstrated     

硬件描述语言VHDL及其应用

ＶＨＤＬ是一种超高速ＶＬＳＩ硬件描述语言，能对集成电路的功能和结构进行描述，用ＣＡＤ软件将其编译和转换，并自动形成线路，概要地介绍了ＶＨＤＬ的设计组织和数据类型，并对ＶＨＤＬ的特点及其在ＶＬＳＩ设计中的应用要点做了一些探讨。     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

A Discrete Fourier-Cosine Transform Chip

An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with the layout. This tool allows mimicking exactly the different representations of the algorithm: software, mask, and chip. This provides an automatic cross-checking at all design stages. The VLSI environment created by this tool, as well as existing powerful CAD tools, made a fast design-time possible.     

A Systematic Approach for Synthesizing VLSI Architectures of Lifting-Based Filter Banks and Transforms

The lifting scheme has become an important tool for designing filter banks and transforms of digital signal processing. Recently, the conventional lifting scheme that concerns the construction of 2-channel filter banks has been extended to $M$-channel filter banks $(M>2)$, bringing up the desirable properties of the lifting scheme to a broader range of applications. Many hand-crafted lifting-based VLSI architectures exist, which mostly concentrate on a single and specific target application having fixed data throughput and resource consumption. However, the reusability of such architectures is limited due to the lack of scalability. To overcome this issue, we present a design methodology for automatic synthesis of VLSI architectures suitable for arbitrary lifting-based $M$-channel filter banks and transforms. The proposed methodology enables high parameterizability in terms of data throughput, resource consumption, and arithmetic precision for the generated architectures. The concept of parameterizing design elements is important for modern system-on-chip design, since it features design space exploration and increases reusability. The proposed methodology is implemented as a high-level compilation tool that generates VLSI architectures at the register transfer level. We present results on the implementation of different architectures that were generated by our tool.      

CAD for nanometer silicon design challenges and success

As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complexity, and manufacturing-aware design techniques control the nanoscale physical effects. In this highlight paper, most nanometer design issues are described and the issues related to the higher level of abstraction are summarized. Process variability can be controlled by statistical design, resolution enhancement, planarity control, and other manufacturing-aware design techniques. Continuously growing problems such as leakage power, signal integrity, and reliability are also discussed. Finally, technology CAD for future nanometer devices is presented. For successful nanometer silicon design, closer cooperation among the design, process technology, mask, and CAD communities are essential.     

一种高效的无线数字通讯的SoC设计方法及其在无线局域网芯片设计中的应用

介绍一种针对高性能的无线数字通讯系统的SoC设计方法。该方法对SoC设计要求高效合理地进行软硬件划分,将划分后的硬件子模块映像到一个高效的多通道总线拓扑结构中以及为不同通道的本地总线设计一个高效自适应的访问协议。同时提出一种全新的专门针对SoC设计、基于总线监控的高效实用的可测性设计方案。以这些设计方法为指导,文章为IEEE 802.11无线局域网的介质访问层和基带控制层的SoC芯片设计提出了一个系统参考解决方案。     

The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

Computer-aided design for integrated circuits: trying to bridge the gap

CAD performance in the field of simulation, testing, and layout is compared to the increase of digital integrated systems complexity. This complexity already exceeds the fundamental limits of existing software, especially in the testing area. On the other hand, fully manual layout of VLSI leads to unreasonably long design times and extremely high risks. This will favor design automation methods in layout. Testability and layout will most likely impose some sacrifice of VLSI overcapacity to a more structured system architecture. This architecture will lead to testable dedicated VLSI system design through the use of automated design software to keep development costs low.     

A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory,Design and Implementation

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. The Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core. The tool can handle generic digital circuits with cell count as high as 15,000 and having the order of 2⁵⁰⁰ states. This is believed to be an improvement of an order of magnitude over results presented in the literature. This methodology enables the designer to tradeoff fault coverage and detection latency against area and power overhead. The design flow using the CAD tool developed is described and results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The methodology is further validated by design, fabrication, and testing of an ASIC in 0.18 μ technology.