Hierarchical design methodologies and tools for VLSI chips

Hierarchical design methods are considered to be a means of managing the VLSI design problem. This paper will consider why this problem exists and discuss alternative means that can be used to arrive at a solution. The merits of design methodologies, with emphasis on hierarchical techniques, will be compared with those of automated design approaches. The discussion of hierarchy will lead to the conclusion that the method requires formal abstraction facilities in order to be effective. Hierarchical design methods permit the creation of a new generation of CAD programs that can both give a designer better support and can be much more efficient than the present generation of tools. An example of such a tool, VOILA, will be given.     

Power conscious CAD tools and methodologies: a perspective

Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design     

CAD tools for ASIC design

Computer aids have been used for both the design and verification of electronic systems for many years. The recent explosion in the complexity of electronic systems that the advent of Very Large Scale Integration (VLSI) has allowed, has made the use of sophisticated computer-aided design tools indispensable. Computer aids will soon also provide key proprietary advantages as semiconductor and system design houses vie for the promising Application-Specific IC (ASIC) market of the next decade. This paper focusses on the techniques critical to both custom and ASIC design, the directions of present research and development for these areas, and future trends. In particular, recent developments in tools for the automated design of combinational logic are reviewed. These techniques include both algorithmic and rule-based approaches.     

A methodology and design tools to support system-level VLSI design

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology     

Issues for low-power CAD tools: A system-level design study

A case study in low-power system-level design is presented. We detail the design of a low-power embedded system, a touchscreen interface device for a personal computer. This device is designed to operate on excess power provided by unused RS232 communication lines. We focus on the design and measurement procedures used to reduce the power requirements of this system to less than 50 mW. Additionally, we highlight opportunities to use system-level design and analysis tools for low-power design and the obstacles that prevented using such tools in this design.     

Technology and design challenges of MOS VLSI

The past decade of MOS technology has been characterized by the scaling of Si-gate LOCOS NMOS to ever smaller geometries. However, NMOS circuits with 1 /spl mu/m geometries will not be achieved by continued direct scaling of this structure. Major changes will be required in the 1-2 /spl mu/m range in terms of: 1) process and structure enhancements that will be required to realize the performance advantages predicted by scaling, and 2) new physical phenomena that will become important in determining MOSFET behavior. The 1-2 /spl mu/m range of NMOS technology is referred to as the `1.25 /spl mu/m discontinuity'. Both aspects of this discontinuity are explored, and some projections for MOS are made for the next decade.     

Computer-aided design tools in chemical engineering process design

This paper reviews the design activity for chemical engineering process design, starting from the earliest step of selecting which products to manufacture and ending with designing the operating procedures for a process plant. At each step we discuss computer-aided design tools which have been or are being developed. Throughout synthesis aids which help make discrete design decisions are contrasted with analysis aids which help to select the proper values for continuous variables. Computer aids are abundant to aid in process design. The future holds promise for an integrated design tool which will aid the engineer from start to finish in his task.     

Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools

In this paper, models of input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on driving CMOS gates. From a detailed analysis of input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, in contrast to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposed to the usual approach that requires numerical estimation of moments. Being fully analytical, the proposed approach permits one to develop models that are extremely simple (i.e. computationally efficient), as well as to gain an insight into the properties of input admittance of RC interconnects.The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65 nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of RC wire input admittance for accurate timing/power estimations in VLSI CAD tools.     

Wire-routing machines—New tools for VLSI physical design

Interconnection of components in a VLSI chip is becoming an increasingly complex problem. In this paper we examine the complexity of the wire routing process and discuss several new approaches to solving the problem using a parallel system architecture. The machines discussed range from compact systems for highly specialized applications to more general designs suited for broader applications. The process speedup due to parallelism and the cost advantage due to the use of large numbers of identical VLSI parts make these new machines practical today.     

Collaborative tools and processes to support software engineering shift work

This paper describes the construction of and early experiences with a software engineering support environment for projects using globally distributed teams. The goals of the project are twofold. Firstly, it aims to construct a pragmatic solution to the problems experienced by widely geographically dispersed groups which collaborate on software development projects. Secondly, it aims to experiment with processes which facilitate software shift work through exploitation of time differences between collaborating groups. The construction of the support environment, known as GWSE (Global Working in Software Engineering) system, is presented, including its architecture and integration with existing workflow, document and project management tools. The use of the GWSE system in a trial development project is then described, including an initial quantitative analysis of the collaboration overheads experienced.     

Managing CAD systems in mechanical design engineering

The results of an investigation into the management and use of CAD systems in ten manufacturing companies are reported. The goal of the research is to understand how engineers and managers perceive CAD systems, how work is restructured when CAD is used, and what barriers prevent the effective use of CAD systems. An introduction to CAD systems is presented, followed by a brief review of the latest literature relating to computer-aided design     

软件工程中的结构化设计方法

针对大型项目开发,为了保证软件产品质量,提高软件开发效率,在进行详细设计、程序设计之前,必须先确定软件总体结构,而结构化设计方法是进行软件总体结构的主要方法。该方法以需求分析阶段获得的数据流图为基础,通过一系列映射,把数据流图变换为软件结构图。在此主要分析了不同类型数据流图如何＂映射＂成软件总体结构,并给出了优化软件结构的规则,及不同类型数据流图＂映射＂成软件总体结构图时顶层、第1层及其下层的转换方法,其可操作性强。     

FPC工程设计软件研发与应用

FPC工程设计是产品可制造性设计（DFM）中最关键的一环,其工程软件的性能优劣决定了工程资料的质量。本文介绍了对工程设计软件进行程序二次开发以弥补软件自身的不足,并通过实例证明使用二次开发程序可最大限度的避免CAM作业人员的人为漏失和软件自身漏洞,提升了工程资料良率及制作效率。     

软件项目建设的可行性研究与工程设计

云计算资源池承载了越来越多的业务应用,传统的应用系统扩容改造变成了“纯软件”的项目.本文结合软件工程的方法与思路,就纯软件项目中设计单位的职责与界面做了分析,并总结了纯软件项目的可行性研究报告与工程设计的编制要点.     

VLSI: linking design and manufacturing

A set of computer-aided design (CAD) tools that predict the effects of various manufacturing steps along with the chip's internal dimensions is described. Called the Process Engineer's Workbench, the system predicts the chip's characteristics, their statistical distribution, and the manufacturing yield likely from any one fabrication process. The tools are even sensitive to the small random variations that increase in significance as devices shrink in size. Workbench can be used to compare its programs' predictions and those of other software tools with actual measurements of devices and processes. Some existing CAD tools are reviewed to highlight the Workbench's advantages, and the features of the latter are examined. Written in C language for a Digital Equipment VAXstation, Workbench was designed to be portable and runs on several other popular workstations. It contains two basic libraries, namely, one of device models, the other of process step models     

Microstrip circular phased array design and development using microwave antenna CAD tools

The complex design and development of a planar multilayer phased array antenna in microstrip technology can be simplified using two commercially available design tools (1) Ansoft Ensemble and (2) HP-EEsof Touchstone. In the approach presented here, Touchstone is used to design RF switches and phase shifters whose scattering parameters are incorporated in Ensemble simulations using its black box tool. Using this approach, Ensemble is able to analyze fully the performance of the radiating and beamforming layers of a phased array prior to its manufacture. This strategy is demonstrated in a design example of a 12-element linearly-polarized circular phased array operating at L band. A comparison between theoretical and experimental results of the array is demonstrated.     

CAD tools for efficient RF/microwave transistor modeling and circuit design

In today’s radiofrequency and microwave communication circuits, there is an ever-increasing demand for higher integration and miniaturization. This trend leads to massive computational tasks during simulation, optimization and statistical analyses, requiring robust modeling tools so that the whole process can be achieved reliably. In this paper, the authors proposed frequency- and time-domain computer-aided design tools that can characterize RF/microwave field effect and heterojunction bipolar transistors and efficiently predict a circuit performance. The proposed tools are demonstrated through examples.