共查询到20条相似文献,搜索用时 15 毫秒
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提出了一种具有软错误自恢复能力的12管SRAM单元。该单元省去了专用的存取管,具有高鲁棒性、低功耗的优点。在65 nm CMOS工艺下,该结构能够完全容忍单点翻转,容忍双点翻转的比例是64.29%,与DICE加固单元相比,双点翻转率降低了30.96%。与DICE、Quatro等相关SRAM加固单元相比,该SRAM单元的读操作电流平均下降了77.91%,动态功耗平均下降了60.21%,静态电流平均下降了44.60%,亚阈值泄漏电流平均下降了27.49%,适用于低功耗场合。 相似文献
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一种低功耗抗辐照加固256kb SRAM的设计 总被引:1,自引:2,他引:1
设计了一个低功耗抗辐照加固的256kbSRAM。为实现抗辐照加固,采用了双向互锁存储单元(DICE)构以及抗辐照加固版图技术。提出了一种新型的灵敏放大器,采用了一种改进的采用虚拟单元的自定时逻辑来实现低功耗。与采用常规控制电路的SRAM相比,读功耗为原来的11%,读取时间加快19%。 相似文献
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提出了一种基于位交错结构的亚阈值10管SRAM单元,实现了电路在超低电压下能稳定地工作,并降低了电路功耗。采用内在读辅助技术消除了读干扰问题,有效提高了低压下的读稳定性。采用削弱单元反馈环路的写辅助技术,极大提高了写能力。该10管SRAM单元可消除半选干扰问题,提高位交错结构的抗软错误能力。在40 nm CMOS工艺下对电路进行了仿真。结果表明,该10管SRAM单元在低压下具有较高的读稳定性和优异的写能力。在0.4 V工作电压下,该10管SRAM单元的写裕度为传统6管单元的14.55倍。 相似文献
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Benton Highsmith Calhoun Anantha P. Chandrakasan 《Solid-State Circuits, IEEE Journal of》2007,42(3):680-688
Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip 相似文献
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A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns. 相似文献
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Ohbayashi S. Yabuuchi M. Kono K. Oda Y. Imaoka S. Usui K. Yonezu T. Iwamoto T. Nii K. Tsukamoto Y. Arakawa M. Uchida T. Okada M. Ishii A. Yoshihara T. Makino H. Ishibashi K. Shinohara H. 《Solid-State Circuits, IEEE Journal of》2008,43(1):96-108
We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mum2 using 65 nm technology. 相似文献
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提出了12管低功耗SRAM加固单元。基于堆叠结构,大幅度降低电路的泄漏电流,有效降低了电路功耗。基于两个稳定结构,可以有效容忍单粒子翻转引起的软错误。Hspice仿真结果表明,与相关加固结构相比,该结构的功耗平均下降31.09%,HSNM平均上升19.91%,RSNM平均上升97.34%,WSNM平均上升15.37%,全工作状态下均具有较高的静态噪声容限,表现出优秀的稳定性能。虽然面积开销平均增加了9.56%,但是,读时间平均下降14.27%,写时间平均下降18.40%,能够满足高速电子设备的需求。 相似文献
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This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC. 相似文献
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This paper presents a 1Kb Sub-threshold SRAM in 180nm CMOS process based on a improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350mV, where the speed is 165KHz and the leakage power is 42nW and the dynamic power is less than 1uW. The designed SRAM can be used in ultra-low-power SoC. 相似文献
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《Microelectronics Journal》2014,45(11):1556-1565
A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to perform write operation without any write assist at VDD=1 V. Monte Carlo simulations for an 8 Kb SRAM (256×32) array indicate that the scalability of operating supply voltage of the proposed cell can be improved by 10% and 21% compared to asymmetric 5T- and standard 6T-SRAM cells; 21% and 53% lower leakage power consumption, respectively. The proposed 6T-SRAM cell design achieves 9% and 19% lower cell area overhead compared with asymmetric 5T- and standard 6T-SRAM cells, respectively. Considering the area overhead for the write assist, replica column and the replica column driver of 2.6%, the overall area reduction in die area is 6.3% and 16.3% as compared with array designs with asymmetric 5T- and standard 6T-SRAM cells. 相似文献
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Bo Zhai Hanson S. Blaauw D. Sylvester D. 《Solid-State Circuits, IEEE Journal of》2008,43(10):2338-2348
In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 mum CMOS technology. We first use detailed simulations to explore the challenges of ultra-low-voltage memory design with a specific emphasis on the implications of variability. We then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime. Measurements of a test chip show that the proposed memory architecture functions from 1.2 V down to 193 mV and provides a 36% improvement in energy consumption over the previously proposed multiplexer-based subthreshold SRAM designs while using only half the area. Adjustable footers and headers are introduced, as well as body bias techniques to extend voltage scaling limits. 相似文献
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本文提出了一种新型的亚阈值10管SRAM单元,在130nm工艺下,本设计的SRAM容量
为6kb,最低可以工作在320mv的电压下。同时一系列的低电压的技术被运用到本SRAM的
设计中,使其能够工作在亚阈值电压下。反短沟效应和反窄沟效应提升了SRAM性能。新型
的脉冲产生电路产生理想的亚阈值脉冲,使得读操作更稳定。浮动的写位线有效地减小了待
机时的漏电。短的读位线使得读操作速度更快和更低功耗。最终流片后的测量表明这系列技
术在亚阈值区都是非常有效的,SRAM在320mv的电压下,工作频率800KHz,消耗功耗
1.94uw。 相似文献
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提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下. 相似文献
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提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下. 相似文献
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Sekiyama A. Seki T. Nagai S. Iwase A. Suzuki N. Hayasaka M. 《Solid-State Circuits, IEEE Journal of》1992,27(5):776-782
A 1-V operating 256-kb full-CMOS SRAM to be used in 1.5-V battery-based applications is presented. A reference word line and address transition detection (ATD) are used as timing control techniques to achieve adjustable timing of critical signals with a 1.5-V battery. The key circuit of the pulse sequence block is the ATD pulse generator circuit. The authors use a newly modified Schmitt trigger delay circuit. To reduce supply line noise in the chip, they needed to lower the peak of bit-line charge-up current. This was done by applying a divided word-line technique and a newly adopted staggered bit-line equalizing pulse technique. The design used a single-polysilicon and double-aluminum process with a full-CMOS memory cell of 8.5 μm×12.8 μm. The chip size is 6.0 mm×9.0 mm 相似文献