Modified feedback ECL gate for Gb/s applications

This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference voltage and finds application in digital optical links in which data is typically transmitted single ended. The gate is compared with FECL and ECL gates, and its application to realize logic functions is discussed. A 6-Gb/s series gated decision circuit and a 2-Gbaud/s four-channel optical receiver array employing modified FECL gates are also described     

HANGMAN Gb/s network

The design and implementation of the Hewlett-Packard active node gigabit-per-second metropolitan area network (HANGMAN) prototype network are discussed. The three main areas addressed are the physical-layer transmission system, the MAC sublayer protocols, and the architecture of the network interface unit. It is shown that low-cost gigabit-per-second transmission systems are practical, particularly in the local area environment where network links are typically limited to a few hundred meters. A MAC protocol that provides a synchronous service as well as the conventional asynchronous data service is described. The node architecture is presented and the way in which a single node can support multiple concurrent physical connections and how this architecture might be used in the future to develop high-performance protocol implementations are also discussed     

Electro-optic polymer-based modulator design and performance for 40 Gb/s system applications

We investigate the potential performance of polymer-based electro-optic (EO) modulators for high-speed systems at 40 Gb/s and beyond. General strategies and specific designs are presented to reduce the modulator half-wave drive voltage while maintaining a broadband response. In addition, we consider practical system requirements that may allow the relaxation of certain modulator design parameters to further improve performance. Designs are presented that may enable a 3-dB electrical bandwidth of 30 GHz with a single-ended half-wave drive voltage of /spl sim/1.6 V for 1.3-/spl mu/m light assuming an effective EO coefficient of 30 pm/V in the waveguide core.     

10Gb/s光网络向40/100G b/s演进的扩容方法

随着需求的增长,业务提供商一直都面临着光网络带宽扩容的压力.在新的技术条件下,以往靠增加网络规模来进行扩容的常规方法已经受到越来越多的局限.文章从常规带宽扩容手段的局限性入手,介绍和分析了DP-QPSK等当前热门的带宽扩容技术在光通信网络由10Gb/s向40/100Gb/s演进过程中的广阔前景及存在的不足.     

基于10 Gb/s传输链路的40 Gb/s光传输实验研究

基于中国自然科学基金网(NSFCNet)的400 km×10 Gb/s光传输链路实现了40 Gb/s光传输,没有出现误码率(BER)平台,说明在常规的中短距离10 Gb/s系统可以直接升级至40 Gb/s系统,而不需要升级传输链路。但是,由于相对10 Gb/s系统而言40 Gb/s系统的色散容限非常小,在升级时必须精确补偿原有链路的色散,在接收机前一般需要加可调色散补偿单元。同时,还分析了光纤注入功率对系统性能的影响,结果表明在设计这种由10 Gb/s向40 Gb/s升级的系统时,不仅要考虑信号带宽增加带来信噪比要求的提高,而且必须充分考虑光纤非线性的影响。     

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

10Gb/s OEIC光接收机前端及3.125Gb/s限幅放大器

摘要：基于南京电子器件研究所Φ76mm GaAs pHEMT工艺,研制了10Gb/s OEIC光接收机前端,并首次采用耗尽型PHEMT设计并实现了限幅放大器。借助模拟软件ATLAS建立并优化了器件模型,组成形式为MSM光探测器和电流模跨阻放大器,探测器带宽超过10GHz,电容约3fF/μm,光敏面积50×50μm2,整个芯片面积1511μm×666μm。限幅放大器采用无源电感扩展带宽,并借助三维电磁仿真软件HFSS进行模拟仿真。限幅放大器芯片面积1950μm×1910μm,在3.125Gb/s传输速率下,分别输入10mVpp和500mVpp,可以得到500mVpp恒定输出摆幅。     

16 Gb/s GaN数模转换器芯片

<正>南京电子器件研究所基于76.2 mm(3英寸)0.1μm Ga N工艺,采用f_t/f_(max)分别为100 GHz/165 GHz的耗尽型晶体管设计,首次研制出16 Gb/s的3 bit DAC芯片。该芯片内核面积约为1.20 mm×0.15 mm。图1为芯片照片,包括驱动及内核电路。图2为芯片400 Mb/s刷新率时输出三角波测试结果。图3为芯片最高16 Gb/s刷新率时输出测试结果。     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

CMOS 5 Gb/s串行接收器

设计了一个使用0.13μm CMOS工艺制造的低电压低功耗串行接收器。它的核心电路工作电压为1V,工作频率范围从2.5 GHz到5 GHz。接收器包括两个1:20的解串器、一个输入信号预放大器以及时钟恢复电路。在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度。测试表明,接收器功耗45 mW。接收器输入信号眼图闭合0.5UI,信号差分峰-峰值150 mV条件下误码率小于10~(-12)。接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。     

Eight-channel p-i-n/HBT monolithic receiver array at 2.5 Gb/s perchannel for WDM applications

We report a monolithic chip incorporating an eight channel p-i-n/HBT photoreceiver array designed for multichannel WDM applications. The p-i-n photodetectors are edge illuminated and centered at a 250 μm pitch for mating with either ribbon fiber connectors or waveguide demultiplexers. Each channel operates at 2.5 Gb/s with an electrical crosstalk of -20 dB between adjacent channels. The average sensitivity of each receiver in the array was measured to be (-20±1) dBm for a bit error rate of 10^-9 at a wavelength of 1.5 μm     

Bandwidth virtualization enables long-haul WDM transport of 40 Gb/s and 100 Gb/s services

This article describes how bandwidth virtualization can enable transmission of ultra-high bandwidth 40 Gb/s and 100 Gb/s services over existing optical transport networks independently of the underlying network infrastructure. An overview of the technology alternatives available to enable high-bandwidth service transport is provided, along with a discussion of the relative merits of different approaches. The authors describe how wavelength division multiplexing, using large- scale photonic integrated circuits combined with the use of a digital virtual concatenation mapping protocol, can be used to enable decoupling of 40 Gb/s and 100 Gb/s service provisioning from the underlying optical link engineering, thereby enabling bandwidth virtualization. Real-world implementation examples of bandwidth virtualization are provided, including 40 Gb/s service transmission over a 2000-km fiber link with 65 ps of peak PMD, a field trial of 40 Gb/s service transmission over an 8477-km trans-oceanic network, and finally a field trial of a pre-standard 100 gigabit Ethernet service transmission over a 4000-km terrestrial long-haul network.     

Wavelength shift keying modulation up to 35 Gb/s with wavelength tone reuse to multiplex two 40 Gb/s DPSK signals

Fast optical frequency shift keying or wavelength shift keying (WSK) modulation offers advantageous features for applications in long haul communications and in optical labeling for packet routing. This includes simple demodulation by optical filtering and constant amplitude envelope providing tolerance to fiber nonlinear effects during transmission. In this paper we report on the generation of WSK signals up to 35 Gb/s with reuse of the wavelength tones for polarization multiplexing two independent 40 Gb/s DPSK signals. Transmission over a 50 km fiber link of the resultant three channel signal is also reported.     

Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications

A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f _T 0.4 μm Si bipolar process. The circuit provides features such as bit-rotation control, clock enable control, outputs aligned in time, and phase aligner for clock signals. It operates up to 14 Gb/s (14 GHz) with a phase margin of ⩾250°. The power consumption is 2 W with a -4.5 V supply. 1:16-demultiplexer operation is demonstrated on the basis of 1:4-demultiplexer IC's at 10 Gb/s     

Photonic access node using optical code-based label processing andits applications to optical data networking

An ultrahigh-speed photonic access node using optical code-based photonic add-drop multiplexing (PADM) and its novel applications to optical data networking are proposed. PADM processes a photonic label of packet, which is mapped onto an optical code, and adds-drops the packet from or to the node, or bypasses the node. PADM is distinct from conventional wavelength ADM (WADM) in that it can handle traffic on a packet-by-packet basis. In the application of PADM to optical data networking, pseudo-time division multiple access (TDMA) and rate-controlled asynchronous access are proposed. The analyses and their numerical simulations of the performances are presented. The simulation results demonstrate low packet-loss probability. Their optical implementations are also demonstrated, in which exploit parallel photonic label processing shows the applicability of proposed optical data networking in an ultrahigh-speed regime     

24万兆比特每秒激光器/光调制器驱动电路

一种应用于高速光纤通讯系统的激光二极管／调制器的单片集成驱动电路已开发成功。该电路的制造使用了0．2μm PHEMT工艺,它的工作信号带宽超过12GHz。在12Gb／s速率下测得了摆幅峰值为3．4V的输出信号眼图。基于实验结果,我们判断该电路的最大工作速率超过24Gb／s。该驱动器电路使用单电源-4．5V供电,功耗小于1．8W。     

2.5Gb/s混合集成光发射机

介绍了适用于光纤通信系统且具有完全自主知识产权的混合集成光发射机的研制.该发射机采用薄膜电路和激光焊接耦合技术将高速集成电路和光电子器件进行混合集成,其中高速集成电路是采用0.35μm硅CMOS工艺实现的单片4∶1复接器加激光驱动器芯片,光电子器件是采用湿法腐蚀、聚合物平坦和lift-off等技术实现的激光器芯片,最终混合集成模块采用蝶形管壳进行封装,体积小、性能优良.该发射机工作速率为2.5Gb/s,波长为1550nm,输出光功率为5.5dBm,消光比为9.4dB.     

2.5Gb/s限幅放大器设计

文章采用TSMC 0．35μmSiGe工艺实现了数据率达到2．5Gh／s的光纤通道限幅放大器。限幅放大器信号通道利用多级放大方式，降低了输出信号上升／下降时间，减小了级间驱动能力不匹配对信号完整性的影响：通过负反馈环路消除了信号通道上的偏移电压，采用独特的迟滞技术，使检测电路的迟滞对外接电阻变化不敏感。仿真结果证明设计方法是有效的。