Analysis of Snapback Phenomena in VDMOS Transistor having the High Second Breakdown Current: A High ESD Mechanism Analysis

We proposed the balanced vertical double - diffused MOS (B-VDMOS) transistor. The B-VDMOS transistor is not destroyed by avalanche breakdown and acquires the high second breakdown current. Owing to the high second breakdown current, the B-VDMOS transistor has high electrostatic discharge (ESD) robustness. This paper presents the mechanism of the snapback phenomena and clarifies the cause that the B-VDMOS transistor has the high second breakdown current. We find the cause that current does not become concentrated even after avalanche breakdown in the B-VDMOS transistor. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A modified LDMOS device with improved ESD protection performance

A modified lateral‐diffusion metal–oxide–semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high‐voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon‐controlled rectifier (LDMOS‐SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS‐SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.     

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

We propose a novel deep gate lateral double diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in partial silicon-on-insulator (PSOI) technology for achieving high breakdown voltage and reduced power dissipation. In the proposed device, an N⁺ well is inserted in the buried oxide under the drain region. By optimizing the N⁺ well and the lateral distance between the buried oxide and the left side of the device, the electric field is modified. Therefore, the breakdown voltage improves. Also, the PSOI technology used in the proposed structure has a significant effect on reducing the lattice temperature. Our simulation results show that the proposed structure improves the breakdown voltage by about 67.5% and reduces the specific on-resistance by about 20% in comparison with a conventional LDMOS.

     

Threshold voltage extraction techniques adaptable from sub‐micron CMOS to large‐area oxide TFT technologies

This paper proposed simple and accurate threshold voltage (V _TH ) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub‐micron complementary metal–oxide–semiconductor to large‐area thin‐film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode‐connected load and a current mirror topology, which allow a direct determination of V _TH . As the proposed techniques are experimented with large‐area emerging technologies, which have a stable single type (n‐type) transistor, all the designs employed in this work are confined to only n‐type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal–oxide–semiconductor (65 and 130 nm) and oxide (indium–gallium–zinc–oxide and zinc–tin–oxide) thin‐film transistors. In order to validate the accuracy of the proposed techniques, extracted V _TH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub‐micron to large‐area transistors. Copyright © 2017 John Wiley & Sons, Ltd.     

A novel flash-like all-metal-oxide semiconductor analog-to-digital converter suitable for system on chips systems

The analog-to-digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all-metal-oxide semiconductor (MOS) flash-like analog-to-digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13-μm complementary MOS (CMOS) technology with a power-supply voltage, V_DD, of 1.2 V. The simulation has been conducted on a 5-bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5-bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.     

Multiscale simulation of MOS systems based on high-κ oxides

We report on a multiscale simulation approach that includes both macroscopic drift-diffusion current model and quantum tunneling model. The models are solved together in a self-consistent way inside a single simulation package. As an example, we study the subthreshold transfer characteristics of MOS transistors based on high-κ oxides. We compare the high-κ gates based on HfO₂ and ZrO₂ with a SiO₂ gate of the same equivalent thickness and show the effect of the tunneling current on transistor performance.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

Characterization of defect density created by stress in the gate to?drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5?nm. We show that this phenomenon is accentuated in high stress accumulation V _g=?3?V, V _d=3?V, but more less for stress V _g=V _d=3?V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.     

A TCAD approach for non-linear evaluation of microwave power transistor and its experimental verification by LDMOS

A simulation technique is developed in TCAD to study the non-linear behavior of RF power transistor. The technique is based on semiconductor transport equations to swot up the overall non-linearity’s occurring in RF power transistor. Computational load-pull simulation technique (CLP) developed in our group, is further extended to study the non-linear effects inside the transistor structure by conventional two-tone RF signals, and initial simulations were done in time domain. The technique is helpful to detect, understand the phenomena and its mechanism which can be resolved and improve the transistor performance. By this technique, the third order intermodulation distortion (IMD₃) was observed at different power levels. The technique was successfully implemented on a laterally-diffused field effect transistor (LDMOS). The value of IMD₃ obtained is −22 dBc at 1-dB compression point (P _{1 dB}) while at 10 dB back off the value increases to −36 dBc. Simulation results were experimentally verified by fabricating a power amplifier with the similar LDMOS transistor.     

Proposal of a Hamming distance detector using neuron MOS transistors

A neuron MOS transistor has been proposed which operates more “intelligently” than a conventional MOS transistor. In this paper, we propose a Hamming distance detector with a large noise margin using the neuron MOS transistors. The proposed circuit accepts two bitstreams to be compared in parallel, and makes it possible to determine if the two bitstreams are identical (“exact match”) or if the Hamming distance between the two bitstreams is within a certain range (“near match”). Moreover, the “acceptable” range of the Hamming distance (in the case of “near match”) can be soft‐programmed. The operating characteristics of the circuit are also analyzed in detail. Furthermore, these analyses are fully confirmed by simulation using the circuit analysis program HSPICE. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 155(1): 44–51, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20223     

High‐performance pMOSFETs with high Ge fraction strained SiGe‐heterostructure channel and ultrashallow source/drain formed by selective B‐doped SiGe CVD

The improvement of current drivability and short‐channel effect is very important for ultrasmall MOS device technology. SiGe‐channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super Self‐aligned Shallow junction Electrode (S³E) MOSFETs formed by selective B‐doped SiGe CVD are effective for the suppression of short‐channel effect. In this paper, it is clarified that the (S³E) pMOSFETs with Si_0.65Ge_0.35 channel are realized not only with suppression of punch‐through due to the ultrashallow B‐diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si channel fabricated by the same process conditions. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 165(3): 46–50, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20597     

New RF extrinsic resistances extraction procedure for deep‐submicron MOS transistors

The modeling of MOS transistors used for RF applications needs the definition of a lumped equivalent circuit where the intrinsic device and series extrinsic resistances are properly evaluated. The model accuracy depends on the extraction precision of each intrinsic lumped element. In order to determine the intrinsic device behavior, it is necessary to first remove the series extrinsic resistances. For this reason their extraction becomes critical for the modeling of MOS transistors in RF circuit design. Several extraction methods have been proposed; nevertheless, the measurement noise strongly affects the obtained results. The method proposed by Bracale and co‐workers is the most robust extraction procedure against measurement noise, but fails to predict correctly the series extrinsic resistances for deep‐submicron devices. For those reasons, we deeply analyze the method proposed by Bracale in order to understand and then overcome its limitations. Based on those analyses, a robust extraction method for deep‐submicron devices is proposed. Copyright © 2009 John Wiley & Sons, Ltd.     

On the input common‐mode voltage range of CMOS bulk‐driven input stages

In this paper the response of a bulk‐driven MOS Metal‐Oxide‐Semiconductor input stage over the input common‐mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35‐µm CMOS Complementary Metal‐Oxide‐Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source‐bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk‐driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5‐V second‐order operational transconductance amplifier (OTA)‐C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.     

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

In this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley & Sons, Ltd.     

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-line-pulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5- mum high-voltage complementary MOS process. Such ESD-enhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 mum, the machine-model ESD levels of the HVPSCR are as high as 1100,1300, and 1900 V, respectively.     

0.5‐V fractional‐order companding filters

Novel configurations of fractional‐order filter topologies, realized through the employment of the concept of companding filtering, are introduced in this paper. As a first step, the design procedure is presented in a systematic algorithmic way, while in the next step, the basic building blocks of sinh‐domain and log‐domain integrators are presented. Because of the employment of metal–oxide–semiconductor (MOS) transistors operated in the subthreshold region, the derived filter structures offer the capability for operation in an ultra‐low‐voltage environment. In addition, because of the offered resistorless realizations, the proposed topologies are reconfigurable, in the sense that the order of the filter could be chosen through appropriate bias current sources. The performance of the derived fractional‐order filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180‐nm complementary MOS (CMOS) process. Copyright © 2014 John Wiley & Sons, Ltd.