Fully integrated CMOS UWB pulse generator

The design of a fully integrated CMOS ultra-wideband (UWB) pulse generator for the 3.1-10.6 GHz frequency band is presented. The pulse generation is based on the filter impulse response technique. With such a technique, the pulse matches the FCC mask with no need for an expensive external filter. The layout of this circuit in a 0.13 mum CMOS technology shows a surface area of less than 0.57 mm² and a power consumption of around 20 mW     

A high precision Doppler radar based on optical fiber delay loops

The proposed theory shows that, by using optical fiber delay lines or loops, it is no longer necessary to compress pulses with matched filters for optimum detection and it is possible to suppress interference from undesirable zones. The suppression leads to lessening of Doppler and range ambiguity. The theory further shows that it is feasible to measure Doppler beating with high precision based on a single pulse. Thus, with a single pulse, there is no Doppler and range ambiguity; interference from undesirable range zones due to Doppler range fold-over will no longer present; and the troublesome ground clutter problem would be greatly suppressed. The high precision Doppler beating provides a mechanism to reveal intrinsic characteristics of a target without time average blurring or masking. New information can be acquired on targets of interest for purpose of passive identification.     

Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

适于视频应用的高数据传输率集成CMOS收发机

这篇文章给出了一个5GHz CMOS射频收发机的设计方案。此设计采用0.18微米射频CMOS加工工艺,集合了最新IEEE802.11n的特性例如多输入多输出技术的专利协议以及其他无线技术,可提供应用在家庭环境中的实时高清电视数据的无线高速传输。设计频率涵盖了从4.9GHz到5.9GHz的ISM频带,每个射频信道的频宽为20MHz。收发机采用了直接上变频发射器和低中频接收器的结构。在没有片上校准的情况下,设计采用双正交直接上变频混频器,得到了超过35dB的镜像抑制。测试结果得到6dB接收机噪声系数以及在-3dBm输出功率时得到发射机EVM结果优于33dB。     

An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A high-resolution time interpolator based on a delay locked loopand an RC delay line

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7-μm CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology     

An integrated CMOS time interval measurement system withsubnanosecond resolution for the WA-98 calorimeter

The time interval measurement system of the WA-98 calorimeter is presented. This system consists of a constant fraction discriminator (CFD), a variable delay circuit, a time-to-amplitude converter (TAC), and a Wilkinson analog-to-digital converter (ADC) all realized in a 1.2-μm N-well CMOS process. These circuits measured the time interval between a reference logic signal and a photomultiplier tube (PMT) signal that had amplitude variations of 100:1 and 10-ns rise and fall times. The system operated over the interval range from 2 ns to 200 ns with a resolution of ~±300 ps including all walk and jitter components. The variable delay circuit allowed the CFD output to be delayed by up to 1 μs with a jitter component of ~0.04% of the delay setting. These circuits operated with a 5-V power supply. Although this application was in nuclear physics instrumentation, these circuits could also be useful in other scientific measurements, medical imaging, automatic test equipment, ranging systems, and industrial electronics     

A fully integrated timing generator for the picturephone video-telephone camera

All the timing intervals necessary for a video-telephone camera have been derived from a multivibrator oscillator by a digital process. These include camera blanking, horizontal and vertical sync, sweep triggering, clamp disable, and locked 2:1 interlace. The timing generator consists of a multivibrator and a pulse-delaying circuit using tantalum integrated RC timing elements and silicon integrated circuits. Output signals are derived digitally using resistor-transistor logic, which best meet the requirements of small size, low power, and producibility while providing adequate noise margin. These logic design considerations are discussed. The complete timing generator has been realized using five beam-leaded silicon and two tantalum integrated circuits including 217 transistors, 345 resistors, and capacitors totaling 4000 pF, all mounted on one square inch of ceramic.     

Clock aligner based on delay locked loop with double edge synchronization

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz.     

基于现场可编程门阵列的数控延时器的设计

给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法.首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度.延时器的外部接口仿照AD9501设计.     

A HIGH RESOLUTION TIME DELAY ESTIMATION BASED ON THE MAXIMUM ENTROPY POWER SPECTRUM ESTIMATON

Multipath time delay estimation is constrained by the width of the signal correlation function when using correlation based methods. This paper obtains a high resolution time delay estimation by introducing Burg algorithm and Marple algorithm of the maximum entropy power spectral estimation to non-resolvable multipath time delay estimatoin. The principles, the performaces and the results of computer simulation are given.     

CMOS delay time model based on weighted peak current

The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results     

Low power,high resolution CMOS variable-delay element

This letter proposes a novel CMOS variable-delay element (VDE). It employs a RC-based differentiator to control the pMOS transistor of a CMOS inverter, whose delay time becomes dependent on the time constant RC. By implementing the RC differentiator with transistor components, the delay can be controlled by variations of both R and C, for fine and coarse delay tuning, respectively. Simulated results show good delay linearity, high resolution and low power consumption for the proposed circuit.     

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-μm CMOS process are given. The circuit uses a quiescent supply current of 0.2 μA and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies     

An integrated CMOS interface for lambda sensor

Automotive pollution can be reduced by suitably controlling the mixture that is fed to the cylinders. This can be performed by means of a feedback loop including a lambda sond and a processing unit which controls the electronic fuel injectors. This paper describes a CMOS interface which adapts the output signal of a lambda sensor to allow its feeding into the processing unit. It provides a differential to a single-ended conversion with a good common mode rejection, a level shifting around a given reference voltage, and an accurate voltage gain. Both design considerations and the measurements performed on an integrated test structure are presented. The measured variation of the large-signal voltage gain for an input signal of 0 to 1 V is within ±5% when the input common mode voltage ranges from -1 V to 1 V with respect to the negative supply voltage. An output voltage with a precision within ±1 mV is obtained in the presence of an input voltage corresponding to the stochiometric composition of the mixture     

An integrated CMOS micromechanical resonator high-Q oscillator

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed μresonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators     

An integrated pre-access architecture for CMOS SRAM

A proposed architecture for CMOS SRAM, random pre-access memory (RPM), allows any single word address to provide simultaneous access to multiple consecutive words starting at the given address. RPM has this pre-access feature integrated into its circuit design in order to minimize access time and increase organizational flexibility. A technique for implementing RPMs of practical size is described, and the characteristics of the memory are examined. Integrating its pre-access function in a CMOS SRAM results in no significant access time penalty, and an area cost of 2% to 8%, depending on the memory organization and size. This architecture is well suited to integrated memory whose requirements necessitate unaligned, multiword access with minimal delay penalty and no power-of-two access restrictions. In particular, such memory finds application in the instruction caches of high-performance superscalar processors, since these require multiple instruction prefetches in a single cycle     

基于新型延迟电路的CMOS片上温度传感器

为在较大温度范围内实现高精度的片上温度检测,提出一种基于新型延迟电路的CMOS时域温度传感器。该传感器以新型延迟电路为基础,利用二极管连接的双极结型晶体管（BJT）生成PWM信号,相较于其它时域温度传感器,仅需要单一偏置电流以及比较器就可生成PWM信号;利用简易的数字计数器可确定占空比,且占空比会被转换成数字值;传感器设计采用了0.18 μm CMOS技术。实际测试结果显示,相较于其它类似传感器,提出的传感器在较宽的温度范围内精确度较高;在两个温度点上进行数字校准之后,在0℃~125℃范围内的精确度为±0.1℃;电源为1.5V时,此传感器仅消耗了2.48 μA,功耗为3.8 μW。 关键词：时域温度传感器;延迟电路;低电压低功率;时间数字转换器（TDC）