Fully integrated CMOS UWB pulse generator

The design of a fully integrated CMOS ultra-wideband (UWB) pulse generator for the 3.1-10.6 GHz frequency band is presented. The pulse generation is based on the filter impulse response technique. With such a technique, the pulse matches the FCC mask with no need for an expensive external filter. The layout of this circuit in a 0.13 mum CMOS technology shows a surface area of less than 0.57 mm² and a power consumption of around 20 mW     

A high precision Doppler radar based on optical fiber delay loops

The proposed theory shows that, by using optical fiber delay lines or loops, it is no longer necessary to compress pulses with matched filters for optimum detection and it is possible to suppress interference from undesirable zones. The suppression leads to lessening of Doppler and range ambiguity. The theory further shows that it is feasible to measure Doppler beating with high precision based on a single pulse. Thus, with a single pulse, there is no Doppler and range ambiguity; interference from undesirable range zones due to Doppler range fold-over will no longer present; and the troublesome ground clutter problem would be greatly suppressed. The high precision Doppler beating provides a mechanism to reveal intrinsic characteristics of a target without time average blurring or masking. New information can be acquired on targets of interest for purpose of passive identification.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A high-resolution time interpolator based on a delay locked loopand an RC delay line

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7-μm CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology     

An integrated CMOS time interval measurement system withsubnanosecond resolution for the WA-98 calorimeter

The time interval measurement system of the WA-98 calorimeter is presented. This system consists of a constant fraction discriminator (CFD), a variable delay circuit, a time-to-amplitude converter (TAC), and a Wilkinson analog-to-digital converter (ADC) all realized in a 1.2-μm N-well CMOS process. These circuits measured the time interval between a reference logic signal and a photomultiplier tube (PMT) signal that had amplitude variations of 100:1 and 10-ns rise and fall times. The system operated over the interval range from 2 ns to 200 ns with a resolution of ~±300 ps including all walk and jitter components. The variable delay circuit allowed the CFD output to be delayed by up to 1 μs with a jitter component of ~0.04% of the delay setting. These circuits operated with a 5-V power supply. Although this application was in nuclear physics instrumentation, these circuits could also be useful in other scientific measurements, medical imaging, automatic test equipment, ranging systems, and industrial electronics     

A fully integrated timing generator for the picturephone video-telephone camera

All the timing intervals necessary for a video-telephone camera have been derived from a multivibrator oscillator by a digital process. These include camera blanking, horizontal and vertical sync, sweep triggering, clamp disable, and locked 2:1 interlace. The timing generator consists of a multivibrator and a pulse-delaying circuit using tantalum integrated RC timing elements and silicon integrated circuits. Output signals are derived digitally using resistor-transistor logic, which best meet the requirements of small size, low power, and producibility while providing adequate noise margin. These logic design considerations are discussed. The complete timing generator has been realized using five beam-leaded silicon and two tantalum integrated circuits including 217 transistors, 345 resistors, and capacitors totaling 4000 pF, all mounted on one square inch of ceramic.     

基于现场可编程门阵列的数控延时器的设计

给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法.首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度.延时器的外部接口仿照AD9501设计.     

Clock aligner based on delay locked loop with double edge synchronization

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz.     

CMOS delay time model based on weighted peak current

The authors propose a new CMOS delay time model with the configuration ratio, the input slope and the load condition taken into account. This model is based on the optimally weighted switching peak current. The delay equations are computationally effective and the error is typically within 10% of SPICE results     

Low power,high resolution CMOS variable-delay element

This letter proposes a novel CMOS variable-delay element (VDE). It employs a RC-based differentiator to control the pMOS transistor of a CMOS inverter, whose delay time becomes dependent on the time constant RC. By implementing the RC differentiator with transistor components, the delay can be controlled by variations of both R and C, for fine and coarse delay tuning, respectively. Simulated results show good delay linearity, high resolution and low power consumption for the proposed circuit.     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

An integrated pre-access architecture for CMOS SRAM

A proposed architecture for CMOS SRAM, random pre-access memory (RPM), allows any single word address to provide simultaneous access to multiple consecutive words starting at the given address. RPM has this pre-access feature integrated into its circuit design in order to minimize access time and increase organizational flexibility. A technique for implementing RPMs of practical size is described, and the characteristics of the memory are examined. Integrating its pre-access function in a CMOS SRAM results in no significant access time penalty, and an area cost of 2% to 8%, depending on the memory organization and size. This architecture is well suited to integrated memory whose requirements necessitate unaligned, multiword access with minimal delay penalty and no power-of-two access restrictions. In particular, such memory finds application in the instruction caches of high-performance superscalar processors, since these require multiple instruction prefetches in a single cycle     

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-μm CMOS process are given. The circuit uses a quiescent supply current of 0.2 μA and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies     

An integrated CMOS micromechanical resonator high-Q oscillator

A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed μresonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators     

An integrated CMOS interface for lambda sensor

Automotive pollution can be reduced by suitably controlling the mixture that is fed to the cylinders. This can be performed by means of a feedback loop including a lambda sond and a processing unit which controls the electronic fuel injectors. This paper describes a CMOS interface which adapts the output signal of a lambda sensor to allow its feeding into the processing unit. It provides a differential to a single-ended conversion with a good common mode rejection, a level shifting around a given reference voltage, and an accurate voltage gain. Both design considerations and the measurements performed on an integrated test structure are presented. The measured variation of the large-signal voltage gain for an input signal of 0 to 1 V is within ±5% when the input common mode voltage ranges from -1 V to 1 V with respect to the negative supply voltage. An output voltage with a precision within ±1 mV is obtained in the presence of an input voltage corresponding to the stochiometric composition of the mixture     

Low power clock generator based on area-reduced interleavedsynchronous mirror delay

A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD     

一种基于特征向量法的高分辨率GPS多路径信号延迟估计方法

多路径原理和干扰抑制是在GPS信号捕获、跟踪和高精度定位中的一个研究热点.延迟时间是多路径信号分析中的一个重要参数,相关延迟估计法是一种基本的估计方法,但是对于GPS多路径信号,它的分辨率有限.在对相关延迟估计方法分析的基础上,给出了一种基于特征向量分解的高分辨率延迟估计方法.首先利用互功率谱把时域的延迟变换到频域的频移,然后把求得的功率谱等效为一个时间序列,再利用特征向量法对该时间序列求功率谱.该功率谱估计方法是一种基于信号子空间和噪声子空间的估计方法,具有高的频率分辨率,从而可以实现对延迟时间的高分辨率估计.     

ANN based CMOS ASIC design for improved temperature-drift compensation of piezoresistive micro-machined high resolution pressure sensor

The paper investigates the temperature-drift compensation of a high resolution piezoresistive pressure sensor using ANN based on conventional neuron model as also the inverse delayed function model of neuron. Using the delayed neuron model, an improvement in temperature-drift compensation has been obtained compared to the conventional neuron model. The CMOS analog ASIC design of a feed forward neural network using the inverse delayed function model of self connectionless neuron for the precise temperature-drift compensation has been presented. The inverse tan-sigmoid function is realized in CMOS implementation by Gilbert multiplier, differential adder and a cubing circuit. The entire design of the circuit has been done using AMS 0.35 μm CMOS model and simulated using Mentor Graphics ELDO simulator. Using the inverse delayed function model of neuron a mean square error of the order of 10⁻⁷ of the neural network has been obtained against a mean square error of the order of 10⁻³ using conventional neuron model for the same architecture of ANN. This brings down the error from 9% for uncompensated sensor to 0.1% only for compensated sensor using the delayed model of neuron in the temperature range of 0-70 °C. Using conventional neuron based ANN compensation, the error is reduced to 1% error.     

基于集成运放的信号发生器设计与仿真

信号发生器在电子电路实验和设备检测中具有十分广泛的用途。本文介绍了一种基于LM301集成运放信号发生器的设计方法,其中信号产生电路模块由积分器和比较器构成,并利用差分放大器的差模传输特性对信号变换,从而输出三角波、方波和正弦波。最后通过Protel99对电路进行仿真,仿真结果表明所设计电路完全满足设计要求。本设计具有输...