A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Expressions

Accurate modeling of the on-chip inductor is essential for the design of high-speed, low-power, and low-noise radio-frequency integrated circuits. The conventional model has a measurable discrepancy as the current flowing in the substrate is not correctly considered. The substrate-coupled inductor model, however, considers the losses generated in both the vertical and horizontal directions. This model gives an intelligent explanation of the reduction in equivalent resistance between terminals with increasing frequency as well as the inductance and quality factor (Q-factor). In order to implement a fully scalable model, the circuit elements in the substrate-coupled inductor model are expressed as monomial equations in terms of physical geometry. These equations consider the physical implications of the parameters as well as employing a mathematical fit for extrapolation. Measurements are made on inductors fabricated using a standard 0.35-mum CMOS process and a 0.15-mum silicon-on-insulator CMOS process to successfully verify this model     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

A simple parameter extraction method of spiral on-chip inductors

Accurate measurement and parameter extraction for spiral inductors are very important in monolithic microwave integrated circuit (MMIC) design. In this paper, we have proposed an easy and simple model parameter extraction method of wide-band on-chip inductor. The simple extraction methodology is applied to extract parameters from the measured S-parameters of spiral inductors fabricated with 0.18-/spl mu/m CMOS technology. Model prediction shows excellent agreement with the measured data over a wide frequency region. Also, the model can be easily integrated in SPICE-compatible simulators because all the elements are frequency independent. This method will provide practical and useful circuit parameters for MMIC design.     

双层螺旋RF MEMS电感的模拟与设计

分析了双层螺旋电感的等效电路模型,研究了一种与传统CMOS工艺兼容的MEMS工艺,通过腐蚀电感结构下的硅衬底使电感悬空.利用HFSS软件对一些双层螺旋微电感进行了模拟,模拟结果表明,相比传统单层电感,双层电感可以减少60%的芯片面积,10nH的电感也只需要很小的面积,经过MEMS后处理的双层螺旋电感的最大Q值都超过了20.     

A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors

A novel compact model for on-chip vertically coiled spiral inductors is presented. The vertical metal coils are modeled by a ladder network consisting of ideal inductors and resistors. The skin and proximity effects are taken into consideration. The capacitive parasitics between relevant metal layers are modeled. A method to analytically extract the model parameters is proposed. The model prediction shows excellent agreement between the data from both simulation and measurement over the frequency range of 0.1–66.1 GHz, for a vertically coiled spiral inductor manufactured in TSMC 90 nm RF CMOS technology.     

A Simple Model Parameter Extraction Methodology for an On‐Chip Spiral Inductor

In this letter, a simple model parameter extraction methodology for an on‐chip spiral inductor is proposed based on a wide‐band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide‐band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using 0.18 µm CMOS technology.     

基于改进1-π拓扑结构的螺旋电感可扩展模型

随着射频集成电路空前发展,电感作为射频电路中重要无源器件应用越来越广.目前其仿真模型应用频率范围较窄并且仿真结果与测试结果拟合较差.本文提出了基于0.13μm SOI CMOS工艺的片上螺旋电感修改模型.模型采用了1-π等效电路,包含有表征衬底涡流的RL并联网络并且改进了由趋肤效应引起的金属线圈中涡流的表征.利用数理统计中的回归分析方法,得到扩展模型参数的表达式.制备了13种不同尺寸的片上螺旋电感用于验证模型.本文提出的方法,对不同尺寸的电感在频率达到自谐振频率以上的行为提供了更好的电路解释.     

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.     

CMOS Micromachined Inductors With Structure Supports for RF Mixer Matching Networks

This letter presents the comparison of three novel structure supports for on-chip complementary metal–oxide–semiconductor (CMOS)-based micromachined inductors by using a proposed two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established and calibrated with inductor fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and the mechanical stability. The mixers, with and without micromachined process inductors, are fabricated in a 0.5-$muhbox{m}$ CMOS process and compared in this letter. The measurement results show a 28.12% increase in conversion gain, a 31.7% improvement in third intercept point, and a 44% reduction in the noise figure.      

Design issues for monolithic DC-DC converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.     

硅基平面螺旋电感的等效电路模型和参数提取

针对螺旋电感传统等效电路模型的不足,提出了一种改进形式的集总参数等效电路模型.该等效电路模型能很好地反映出电感参数随频率变化的实际效应,可适用于从低频到自谐振频率的宽频带范围.同时,应用电磁场全波分析方法对CMOS工艺下平面螺旋电感进行仿真分析.从得到的散射参数中提取电感L、Q值及自谐振频率.基于参数优化和曲线拟合技术,给出了等效电路模型中各个元件值的多变量闭合表达式.这些表达式可方便地用于集成电路的设计和优化,从而提高电路设计的性能和效率.     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

Integrated RF components in a SiGe bipolar technology

Several components for the design of monolithic RF transceivers on silicon substrates are presented and discussed. They are integrated in a manufacturable analog SiGe bipolar technology without any significant process alterations. Spiral inductors have inductance values in the range of ~0.15-80 nH with typical maximum quality-factors (Q_max ) of 3-20. The Q_max's are highest if the doping concentration under the inductors is kept minimum. It is shown that the inductor area is an important parameter toward optimization of Q_max at a given frequency. The inductors can be represented in circuit design by a simple lumped-element model. MOS capacitors have Q's of ~20/f (GHz)/C(pF), metal-insulator-metal (MIM) capacitors reach Q's of ~80/f (GHz)/C(pF), and varactors with a 40% tuning range have Q's of ~70/f (GHz)/C(pF). Those devices can he modeled by using lumped elements as well. The accuracy of the modeling is verified by comparing the simulated and the measured high-frequency characteristics of a fully integrated, passive-element bandpass filter     

A simple CMOS-based inductor simulator and frequency performance improvement techniques

In this paper, a new CMOS grounded positive tunable inductor simulator based on using two simple CMOS transconductors and an inverting amplifier is presented. The introduced inductor simulator uses a grounded capacitor; accordingly, it is suitable for integrated circuit (IC) fabrication. In addition a CMOS circuit for realizing negative tunable resistor which can be used for parasitic cancellation in inductor simulators and consequently enhancing their frequency performances is developed. A novel method for providing high-frequency performance improvement of simulated inductors is also introduced. Simulation and experimental results are given to demonstrate the performance of the developed inductor simulator and validity of the proposed frequency performance improvement method.     

A simple wide-band on-chip inductor model for silicon-based RF ICs

In this paper, we developed a simple wide-band inductor model that contains lateral substrate resistance and capacitance to model the decrease in the series resistance at high frequencies related to lateral coupling through the silicon substrate. The model accurately predicts the equivalent series resistance and inductance over a wide-frequency range. Since it has frequency-independent elements, the proposed model can be easily integrated in SPICE-compatible simulators. The proposed model has been verified with measured results of inductors fabricated in a 0.18-/spl mu/m six-metal CMOS process. We also demonstrate the validity of the proposed model for shielded inductors. The proposed model shows excellent agreement with measured data over the whole frequency range.     

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.     

Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested     

Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits

In this brief, three novel structure supports for on-chip CMOS-based micromachined inductors are proposed to improve mechanical stability. The inductors are fabricated using a two-step maskless post-CMOS process. A 3-D electromagnetic inductor simulation model is established for performance analysis of the inductors before fabrication. The proposed inductors are applied in the matching network of the double-balanced Gilbert mixer to improve the performance and mechanical reliability for mobile communication. The mixers with and without micromachined process inductors are fabricated in a 0.5-mum CMOS process. The measurement results show an 18.6% increase in the conversion gain, a 31.7% improvement in the third intercept point (IIP3), and a 25.3% reduction in the noise figure.