一种基于FPGA实现的真随机数发生器

本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。电路为纯数字形式,50MHz采样时钟采得的输出数据可以无需后处理,直接通过随机性测试,且未发现随机性与采样频率存在显著联系。     

一种无记忆的真随机数发生器

基于传统的振荡采样电路,设计了一种无记忆的真随机数发生器,从理论上保证了输出是相互独立的.采用弹性函数作为后处理,以较小的硬件代价改善了随机数的统计性能.用纯数字电路在FPGA平台上实现,并验证了该真随机数发生器的性能.测试结果表明该真随机数发生器具有较高的数据输出率和良好的统计特性,适合应用于密码系统中.     

物理真随机数发生器的设计

为了得到平稳的随机信号,设计了一种应用于智能卡的物理真随机数发生器。采用振荡采样的方法将噪声源产生的抖动噪声转变为随机数。同时,在发生器输出级运用由异或链、线性反馈移位寄存器组成的后处理模块,消除外部干扰导致随机数发生器产生的偏差和自相关性。通过设计在线检测电路,实时检测随机序列的质量。理论研究和仿真测试证明,该方案能生成均匀、彼此独立的随机信号。     

True Random Number Generator With a Metastability-Based Quality Control

We present a metastability-based true random number generator that achieves high entropy and passes NIST randomness tests. The generator grades the probability of randomness regardless of the output bit value by measuring the metastable resolution time. The system determines the original random noise level at the time of metastability and tunes itself to achieve a high probability of randomness. Dynamic control enables the system to respond to deterministic noise and a qualifier module grades the individual metastable events to produce a high-entropy random bit-stream. The grading module allows the user to trade off output bit-rate with the quality of the bit-stream. A fully integrated true random number generator was fabricated in a 0.13 mum bulk CMOS technology with an area of 0.145 mm².     

一种基于噪声的真随机数发生器的ASIC设计与实现

提出了一种应用于密码系统的硬件随机数发生器的ASIC实现,即通过振荡采样把相位噪声转变为随机数.为了使输出平稳,在输出级设计了异或链和伪随机网络.理论研究和仿真测试证明,该方案能生成分布均匀、彼此独立的随机信号.经制版流片后,芯片在1 MHz时钟下输出满足随机性测试的串行随机数.     

利用竞争冒险的真随机数发生器设计

针对真随机数广泛应用的现状,基于振荡器采样和反馈电路竞争冒险机制,分析和设计了一款真随机数发生器。采用VHDL语言为描述工具,以纯数字IP核的形式提供了该发生器,并给出了一种与微控制器OC8051 IP核的挂接方法。选用Ahera Cyclone—Ⅱ FPGA开发板对随机数发生器进行验证,结果表明其逻辑和时序工作稳定,且随机数产生速率可达7．85M／s,完全通过7种随机性检测,可应用于实际的工程开发中。     

Very High-Speed True Random Noise Generator

In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for random bit generation is presented. The proposed circuit topology prevents the degradation of the generated-sequence statistical properties that can be caused by several factors, including the parameter spreading of the technological processes. Experimental results show that, with a final rate of 3 Mbit/s, the circuit is compliant with the most recent security requirements for cryptographic modules issued by the American National Institute of Standards and Technologies.     

一种基于混沌原理的真随机数发生器

选取一维分段线性混沌映射函数设计真随机数发生器的随机源,具体分析了函数中各参数对输出序列随机性和电路稳定性的影响.通过改进函数在混沌吸引盆外的映射关系,成功解决了真随机源电路在各种噪声干扰和器件失配影响下所可能存在的失效问题,显著提高了电路的稳定性.该混沌函数以电压作为迭代变量,电路采用了负反馈形式的运放、采样保持电路和逻辑判断电路等模块,并运用了电荷再分配技术.以该随机源构成的真随机数发生器不但具有理想的随机性,在1M bit/s的输出速率下,平均功耗不超过0.3mW,可广泛应用在SoC等嵌入式环境中.     

量子保密系统真随机源的实现

研究了基于物理随机源的方法产生真随机码：即用基于晶体二极管pn结齐纳击穿电压的随机性产生随机的电平信号,然后利用电压比较器甄别噪声电压,从而获得随机二进制序列,可用于控制量子保密通信系统的位相调制器,从而产生随机量子码。研制的随机二进制码理论上最大码率200kbit／s。     

基于振荡器的高性能真随机数发生器

设计了一种应用于信息安全SoC平台的基于振荡器的高性能真随机数发生器,其利用放大的电阻热噪声来增大慢振荡器的抖动,使得前后两次采样相互独立,提高了序列的随机性能。采用T触发器采样消除快振荡器占空比偏差的影响。真随机数发生器采用TSMC 0.25μm CMOS工艺,输出速率达4Mbps,通过NIST FIPS140-1和SP800-22中的各项测试。芯片面积为0.09mm2,工作电压为2.5V,功耗为4.15mW。     

基于振荡器的真随机数发生器的研究

以基于振荡器的真随机数发生器为研究对象,理论分析了影响随机数发生器输出随机性的关键因素.对影响随机性的因素给出不同的参数选取,并使用Matlab软件对各种条件下输出序列的0/1概率差进行了计算,分别验证了采样时刻、高频占空比等因素对真随机数发生器输出的影响,给出了能够提高基于振荡器采样的真随机数发生器随机性的具体方法.所得的结论对设计一个具体的基于振荡器的真随机数发生器具有明确的指导意义.     

基于混沌的高速随机数发生器

基于混沌的随机数发生器采用了离散时问的决定论混沌系统。决定论混沌的一个本质特征是对初始值的敏感依赖性。由于初始值是一个模拟电路的初值，对于数字测量系统是永远无法逼近或达到的，它的偏差使得测量系统产生的符号序列以后有着充分大的分离，从而使得符号序列不可预知、不可再现，具有真随机的特性。在分析了一类分段线性映射的决定论混沌系统的基本特性后，设计了由开关电容电路等组成的模拟电路。为了保证随机序列的分布特性，针对CMOS电路中主要的噪声，即MOS管的热噪声与闪烁噪声，设计时建立了二种噪声仿真模型；同时为了加快分析的效率和速度，提出了一种快速分析方法。最后，采用NIST标准进行了测试。     

基于FPGA的高速高斯随机数发生器

设计了一个基于FPGA的高速、高性能的高斯随机数发生器。首先简要介绍了以前的一些算法并指出其不足之处。然后阐明了本文的算法：对均匀随机数进行高效的变换以生成非常接近高斯分布的随机数,再依据中心极限定理把两个上述随机数相加得到高斯随机数。算法所需的运算只有RAM的读操作与乘法、加法运算。分析了算法的性能并与其他算法做了对比,证明了本文算法的高效性。最后给出了FPGA实现的系统结构,并分析了所需的硬件资源。     

一种基于流水型ADC的高速真随机数发生器

1.5位每级流水型ADC子单元的传输函数满足混沌映射的特性,通过将子单元的两个数字输出进行异或,改变产生序列的分布特性,即可用来产生独立且均匀分布的随机数.根据这个原理设计实现了一种高速真随机数发生器,并引入了一种新型的高速低功耗预放大锁存比较器.仿真结果表明,在未加任何后处理电路修正的情况下,生成的随机序列即可通过NIST标准随机性检测,输出比特率可达200Mb/s.     

Thermal Noise Random Number Generator Based on LFSR

With the rapid development of cryptography, the strength of security protocols and encryption algorithms consumedly relies on the quality of random number. In many cryptography applications, higher speed is one of the references required. A new security random number generator architecture is presented. Its philosophy architecture is implemented with FPGA, based on the thermal noise and linear feedback shift register（LFSR）. The thermal noise initializes LFSRs and is used as the disturbed source of the system to ensure the unpredictability of the produced random number and improve the security strength of the system. Parallel LFSRs can produce the pseudo-random numbers with long period and higher speed. The proposed architecture can meet the requirements of high quality and high speed in cryptography.     

A Robust Random Number Generator Based on a Differential Current-Mode Chaos

This paper demonstrates a differential current-mode chaos-based circuit used to generate random number sequences, which was implemented on 90-nm CMOS-SOI technology. The proposed design is more suitable for circuit implementation of a chaotic map, and diminishes non-idealities such as asymmetry, offset and low slope values. The differential design also exhibits superior robustness to supply voltage, temperature, and process variations. Behavioral and SPICE simulations are used to show the advantages of the differential chaos circuit in comparison to a single ended version. Furthermore, to validate that the circuit can serve as a white noise generator, a statistical random number generator test, as suggested by the Federal Information Processing Standard (FIPS), was conducted on the simulation results and verified on the hardware. The results of the test demonstrated that the circuit functions with very high robustness.      

一种基于混沌的随机数发生器设计及其IC实现

在密码学、仿真学以及集成电路测试等许多领域 ,随机数起着重要的作用。在密码学中 ,通常要求所使用的随机数具有不可预测性。基于混沌现象 ,使用开关电容技术 ,用集成电路实现了一种硬件随机数发生器。测试结果表明 ,其产生的序列具有不可预测性 ,可以满足密码学的应用要求。     

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator

Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG.     

Ultra-Low Power Truly Random Number Generator for RFID Tag

This paper proposes low power, low voltage Truly Random Number Generators (TRNG) for Electrical Product Code (EPC Generation 2 Radio Frequency Identification (RFID) tag. Design considerations and trade-offs among randomicity, chip area and power consumption are analyzed according to the special requirements of Gen2 RFID tag. The proposed TRNG circuits consist of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers for post digital processing. These TRNG are implemented in SMIC 0.18 μm CMOS process. And their randomicity performances are verified by the FIPS 140-2 standard for security. One of the TRNG circuits outputs a random bit series at a speed of 40 kHz. Its power consumption is 1.04 μW and chip area is 0.05 mm². The other one has a bit rate at 48 kHz. It has a power consumption of 2.6 μW and chip area of 0.018 mm². The features of low power and small chip area in these TRNG circuits provide a good choice to solve the security and privacy problems in RFID systems.     

基于DES的随机数发生器的实现研究

本文分别从行为级和RTL级实现并且验证了DES电路。在DES的VLSI实现过程中充分考虑了DES的结构特征，采取一系列的优化措施，使得整个电路在速度和面积上取得了较好的效果。最后提出一个适用于IC卡等有嵌入式安全需要的系统中的DES模块的实现方案。