GaN HFET中的能带峰势垒和跨导崩塌北大核心

考虑大沟道电流下外沟道局域电子气慢输运行为破坏沟道电中性,诱生空间电荷导致的能带峰势垒,提出了新的跨导崩塌模型。详细计算了不同栅压和不同沟道电流密度、即不同空间电荷密度下的场效应管能带。引入新的能带峰势垒和沟道电子跨越势垒的动态模型,解释了沟道打开过程中源电阻增大、沟道电子平均速度下降、大沟道电流下跨导下降等各类跨导崩塌行为,解释了场效应管沟道电子速度远低于异质结材料的缘由。运用沟道打开时的异质结充电和大沟道电流激励下空间电荷触发的能带峰势垒模型解释了跨导钟形曲线上升段中的电流崩塌和下降段中的跨导崩塌。深入研究了陷阱和局域电子气的相互作用,解释了可靠性加速寿命试验中的跨导曲线变化。沟道夹断的强负栅压应力产生内沟道逆压电缺陷,减弱栅电压对内沟道电子气的控制和沟道打开时跨导的上升斜率。沟道打开后的大电流应力使局域电子气与晶格碰撞产生热电子缺陷和空间电荷,抬高能带峰势垒引发外沟道堵塞,降低沟道电流,导致阈值电压正移。这一研究证明在场效应管直流和射频工作中的器件性能退化都是由陷阱同局域电子气相互作用产生的,开创了优化设计异质结能带来提高场效应管可靠性的新途径。最后讨论大沟道电流下能带峰势垒引发的外沟道堵塞和跨导崩塌在场效应管研发中的重要作用,提出了在空间电荷区上方设置专用的异质结鳍来平衡内、外沟道能带,解开场效应管中的电流崩塌、跨导崩塌、线性、器件性能退化及3 mm高频工作等难点。     

一种积累型槽栅超势垒二极管

提出了一种积累型槽栅超势垒二极管,该二极管采用N型积累型MOSFET,通过MOSFET的体效应作用降低二极管势垒。当外加很小的正向电压时,在N+区下方以及栅氧化层和N-区界面处形成电子积累的薄层,形成电子电流,进一步降低二极管正向压降;随着外加电压增大,P+区、N-外延区和N+衬底构成的PIN二极管开启,提供大电流。反向阻断时,MOSFET截止,PN结快速耗尽,利用反偏PN结来承担反向耐压。N型积累型MOSFET沟道长度由N+区和N外延区间的N-区长度决定。仿真结果表明,在相同外延层厚度和浓度下,该结构器件的开启电压约为0.23 V,远低于普通PIN二极管的开启电压,较肖特基二极管的开启电压降低约30%,泄漏电流比肖特基二极管小近50倍。     

栅缓冲层对4H碳化硅肖特基势垒场效应晶体管性能的影响

通过在栅极和沟道层间插入一层低掺杂的缓冲层研究了其对肖特基势垒场效应晶体管性能的影响。通过求解一维和二维泊松方程,得到了电流和小信号参数与缓冲层厚度和浓度的依赖关系。当缓冲层厚度为0.15μm时,计算了器件的直流和交流特性;同时仿真了器件的击穿特性。结果表明,电流随缓冲层厚度增加;击穿电压由125V增加到160V;截止频率由20GHz增加到27GHz。     

不同沟道宽长比有机薄膜晶体管性能的研究

以酞菁铜为有源层,二氧化硅为绝缘层,钛/金作为电极,制作了三种不同沟道宽长比的有机薄膜晶体管器件。通过对这三种器件的电学特性进行对比,分析了不同沟道宽长比对器件电学性能的影响。结果表明,沟道宽长比对器件的迁移率影响很小,阈值电压随着宽长比的增大而减小,漏电流随沟道宽长比的增大而增大;当源漏极间电压在一定范围内时,开态电流也随沟道宽长比的增大而增大。     

AlGaN/GaN二维电子气的特性研究

应用 Al Ga N/Ga N异质结中的压电极化和自发极化边界条件自洽求解了薛定谔方程和泊松方程 ,求出了异质结能带和二维电子气分布。研究了势垒层组分比、势垒层宽度、沟道层掺杂和栅电压变化对二维电子气特性的影响。着重研究了栅电压对二维电子气特性的控制作用 ,提出了使用薄势垒和重掺杂沟道的新 HFET结构     

AlGaN/GaN HFET的优化设计

从自洽求解薛定谔方程和泊松方程出发研究了不同掺杂方式下异质结能带和二维电子气的行为。发现掺杂能剪裁异质结能带的弯曲度、控制电子气的二维特性和浓度。在此基础上研究了不同掺杂方式的掺杂效率。通过掺杂和势垒结构的优化设计,得出了用δ掺杂加薄AlN隔离层的结构,既提高了电子气浓度,又保持电子气的强二维特性。从电子气浓度和栅对电子气的控制力度出发,提出了HFET势垒优化设计中的电子气浓度与势垒层厚度乘积规则。依据二维表面态理论,研究了表面态随帽层掺杂结构的变化。从前述乘积规则和表面态变化出发进行了内、外沟道异质结构的优化设计。优化结构既提高了电子气浓度和跨导,降低了欧姆接触电阻,又抑制了电流崩塌。     

AlGaN／GaN二维电子气的特性研究

应用AlGaN/GaN异质结中的压电极化和自发极化边界条件自洽求解了薛定谔方程和泊松方程,求出异质结能带和二维电子气分布。研究了势垒层组分化、势垒层宽度、沟道层掺杂和栅电压变化对二维电子气特性的影响。着重研究了栅电压对二维电子气维性的控制作用,提出了使用薄势垒和重掺杂沟道的新HFET结构。     

GaN HFET沟道中的电子状态转移和非线性研究

从自洽求解薛定谔方程和泊松方程出发研究了大栅压摆动下的沟道电子状态,发现高栅压下电子波函数向势垒层的渗透和激发子带向势垒层的转移是导致跨导下降、线性变差的主要原因。分别研究了势垒层和沟道结构对波函数渗透和电子态转移的影响。通过势垒层和沟道结构的综合设计获得了在大栅压摆动下保持高跨导和线性的优化结构。提出了剪裁二维能带结构的新工艺方案。     

掺杂分布对EPROM编程的影响

在EPROM器件中,栅注入电流Ig对于Si表面的可动电子浓度n和电场E非常敏感。我们用二维电子温度器件模拟程序研究了n、E和Ig与掺杂分布的关系。 我们研究了沟长L=2(μm)、浮置栅氧化层厚度T_(ox)=400(?)的双栅EPROM器件。漏极写入电压采用17V,产生的漏电流为1.2mA。我们在一个等效的MOSFET上调节栅电压,以便使漏电流I_d与这一写电流相等,发现三种不同的沟道分布的浮置栅压(V_(gf))当量为12.8V、13.9V和16V。     

4H-SiC MESFET的特性研究

对4H-SiC MESFET的特性研究发现,在室温下4H-SiC MESFET饱和漏电流的值为0.75A/mm,随着温度的上升,器件的饱和漏电流和跨导一直下降;栅长越短,沟道层掺杂浓度越高,饱和漏电流就越大.300K时器件的击穿电压为209V,计算出来的最大功率密度可达19.22W/mm.这些结果显示了4H-SiC在高温、高压、大功率器件应用中的优势.     

不同AlGaN层厚度的AlGaN/GaN高电子迁移率晶体管的静态特性

利用金属有机化合物气相外延技术研究了AlGaN/GaN高电子迁移率晶体管(HEMT)结构的外延生长及器件制作,重点比较了具有不同AlGaN层厚度的HEMT器件的静态特性.实验发现具有较薄AlGaN隔离层的结构表现出较好的器件特性.栅长为1μm的器件获得了650mA/mm的最大饱和电流密度和100mS/mm的最大跨导.     

Ultrathin InAlN/AlN Barrier HEMT With High Performance in Normally Off Operation

We present GaN-based high electron mobility transistors (HEMTs) with a 2-nm-thin InAlN/AlN barrier capped with highly doped n⁺⁺ GaN. Selective etching of the cap layer results in a well-controllable ultrathin barrier enhancement-mode device with a threshold voltage of +0.7 V. The n⁺⁺ GaN layer provides a 290-Omega/square sheet resistance in the HEMT access region and eliminates current dispersion measured by pulsed IV without requiring additional surface passivation. Devices with a gate length of 0.5-mum exhibit maximum drain current of 800 mA/mm, maximum transconductance of 400 mS/mm, and current cutoff frequency fT of 33.7 GHz. In addition, we demonstrate depletion-mode devices on the same wafer, opening up perspectives for reproducible high-performance InAlN-based digital integrated circuits.     

Short-Channel Effect Limitations on High-Frequency Operation of AlGaN/GaN HEMTs for T-Gate Devices

AlGaN/GaN high-electron mobility transistors (HEMTs) were fabricated on SiC substrates with epitaxial layers grown by multiple suppliers and methods. Devices with gate lengths varying from 0.50 to 0.09 mum were fabricated on each sample. We demonstrate the impact of varying the gate lengths and show that the unity current gain frequency response (f_T) is limited by short-channel effects for all samples measured. We present an empirically based physical model that can predict the expected extrinsic f_T for many combinations of gate length and commonly used barrier layer thickness (t_bar) on silicon nitride passivated T-gated AlGaN/GaN HEMTs. The result is that even typical high-aspect-ratio (gate length to barrier thickness) devices show device performance limitations due to short-channel effects. We present the design tradeoffs and show the parameter space required to achieve optimal frequency performance for GaN technology. These design rules differ from the traditional GaAs technology by requiring a significantly higher aspect ratio to mitigate the short-channel effects.     

Copper gate AlGaN/GaN HEMT with low gate leakage current

Copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current were demonstrated. For comparison, nickel/gold (Ni/Au) gate devices were also fabricated with the same process conditions except the gate metals. Comparable extrinsic transconductance was obtained for the two kinds of devices. At gate voltage of -15 V, typical gate leakage currents are found to be as low as 3.5/spl times/10/sup -8/ A for a Cu-gate device with gate length of 2 /spl mu/m and width of 50 /spl mu/m, which is much lower than that of Ni/Au-gate device. No adhesion problem occurred during these experiments. Gate resistance of Cu-gate is found to be about 60% as that of NiAu. The Schottky barrier height of Cu on n-GaN is 0.18 eV higher than that of Ni/Au obtained from Schottky diode experiments. No Cu diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. These results indicate that copper is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMT.     

Enhanced Gate Swing in InP HEMTs With High Threshold Voltage by Means of InAlAsSb Barrier

We demonstrated the suitability of the InP HEMTs with the InAlAsSb Schottky barrier to realize the high threshold voltage (enhancement mode), low gate current, and low power consumption. This quaternary compound material increases the conduction band discontinuity to the InGaAs channel by introducing only 10% of antimony to InAlAs. The gate current is reduced by an order of the magnitude (or even more) at gate voltage range from 0.4 to 0.8 V. On the other hand, the large conduction band discontinuity causes larger parasitic source and drain resistance, which decreases the extrinsic transconductance. Nevertheless, the high-frequency performance is comparable to the device with the conventional InAlAs barrier layer. Therefore, the InAlAsSb barrier is a promising option for logic applications, which requires reduced gate current. FETs, gate current, high-electron mobility transistors (HEMTs), high frequency.     

InAlN/AlN/GaN HEMT器件特性研究

通过利用MOCVD生长的高质量蓝宝石衬底InAlN/AlN/GaN异质结材料,获得了高的二维电子气面密度,其值为1.65×10<'13>cm<'-2>.通过该结构制备了0.15 μm栅长InAlN/AIN/GaN HEMT器件,获得了相关的电学特性:最大电流密度为1.3A/mm,峰值跨导为260mS/ram,电流增益截...     

Characteristics of Al/sub 2/O/sub 3//AllnN /GaN MOSHEMT

InAlN/GaN is a new heterostructure system for HEMTs with thin barrier layers and high channel current densities well above 1 A/mm. To improve the leakage characteristics of such thin-barrier devices, AlInN/GaN MOSHEMT devices with a 11 nm InAlN barrier and an additional 5 nm Al₂O₃ barrier (deposited by ALD) were fabricated and evaluated. Gate leakage in reverse direction could be reduced by one order of magnitude and the forward gate voltage swing increased to 4 V without gate breakdown. Compared to HEMT devices of similar geometry, no degradation of the current gain cutoff frequency was observed. The results showed that InAlN/GaN FETs with high channel current densities can be realised with low gate leakage characteristics and high structural aspect ratio by insertion of a thin Al₂O ₃ gate dielectric layer     

Trigger sensitivity of transferred electron logic devices

An analysis of the Schottky-barrier gate transferred electron logic devices (TELD's) is developed which gives the trigger sensitivity in terms of the channel pinchoff voltage, normalized channel depletion width under the gate, device subthreshold transconductance, and the value of the external load resistor. The results presented show that the trigger sensitivity increases with increase in doping density, decrease in channel pinchoff voltage, and decrease in gate reverse bias. Furthermore, for the same material parameters (doping density, channel thickness, etc.) device subthreshold transconductance (gm) improves the trigger sensitivity by a factor (1 + gmRL). Device designs based on this analysis should result in improved device performance.     

AlGaN/GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation

AlGaN/GaN HEMTs with a thin InGaN cap layer have been proposed to implement the normally off HEMTs. The key idea is to employ the polarization-induced field in the InGaN cap layer, by which the conduction band is raised, which leads to the normally off operation. The fabricated HEMT with an In_0.2Ga_0.8N cap layer with a thickness of 5 nm showed normally off operation with a threshold voltage of 0.4 V and a maximum transconductance of 85 mS/mm for the device with a 1.9-mum-long gate. By etching off the In_0.2Ga_0.8N cap layer at the access region using gate electrode as an etching mask, the maximum transconductance has increased from 85 to 130 mS/mm due to a reduction of the parasitic source resistance.     

High voltage degradation of GaN High Electron Mobility Transistors on silicon substrate

We have electrically stressed GaN High Electron Mobility Transistors on Si substrate at high voltages. We observe a pattern of device degradation that differs markedly from previous reports in GaN-on-SiC HEMTs. Similarly to these devices, the gate leakage current of GaN-on-Si HEMTs increases by several orders of magnitude at a certain critical voltage and this increase is irreversible. However, in contrast with devices on SiC, the critical voltage varies substantially across the wafer, even over short distances, with values as high as 75 V being observed. In addition, for voltages below the critical voltage, we observe a prominent degradation in the drain current and the source and drain resistances, something not observed in devices on SiC. This degradation is almost completely recoverable under UV illumination. We attribute these results to the high mismatch that exists between GaN and Si that leads to a large concentration of electrically active traps and a lower and non-uniform initial strain in the AlGaN barrier. This is evidenced by observed correlations between threshold voltage and maximum drain current in fresh devices and their corresponding critical voltages.