X-tolerant test response compaction

Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.     

多扫描链测试集的分组标准向量压缩法

针对相容压缩方法对确定位分布不平衡的测试数据集的压缩效果不佳的问题,将测试集按多扫描链结构排列后,根据向量之间相同相容关系的数目将测试集划分为若干组,分别对各组实行相容压缩;再次排列后,用标准向量差分法进行差分,并运用距离标记法对差分向量作第二次压缩.该方法对确定位分布不平衡的测试集有较高的压缩率,且向量差分时所需的循环移位寄存器数目少.     

一种基于扫描链阻塞技术的低费用测试方法

为进一步降低测试功耗及测试应用时间,提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法.该方法考虑前后2个测试向量之间不相容的扫描子链,后一个测试向量可以由扫描输入移入若干位以及前一个测试向量的前若干位组合而成.实验结果表明,该方法能够有效减少测试应用时间,提升效率.     

基于测试向量压缩的多核并行测试

首先整合多个被测芯核的测试集,合并重叠的测试向量以减少测试向量个数,从而缩短了测试应用时间,测试应用时采用总线广播的形式实现并行测试;然后应用多扫描链相容压缩和距离标记方法压缩测试数据,多扫描链相容压缩后,测试向量宽度规则减小,且距离标记法可进一步有效地压缩测试数据量.该方法数据压缩效率高,测试应用时间短,与其他并行测试方法相比具有测试控制过程简单和硬件开销小的突出优点.     

应用向量划分的低功耗确定性BIST方法

提出一种能够与LFSR重播种技术结合的确定性向量生成方法,该方法利用扫描向量中的切片重叠来同时减少确定位数目和跳变数目,可大大降低测试功耗和测试存储.在硬件结构中,用一个译码器来生成控制信号.实验结果表明,对于ISCAS89基准电路,采用文中方法能够减少80%左右的跳变,而只需要原始Mintest测试集25%左右的测试数据存储.     

基于树形解压缩器的低测试数据量方法

提出一种由异或门按照完全二叉树形状排列而成的树形向量解压缩器。该解压缩器的少数输出端需要由大部分的输入端来确定,而且该结构对其输出值的确定关系类似于扫描链中确定位的分布概率,可有效降低测试数据量。实验结果表明,对于ISCAS’89基准电路,该结构最高将测试数据量压缩了77倍。     

基于部分测试向量切分的LFSR重新播种方法

提出一种测试码压缩方法,首先切分测试集中含确定位较多的难以编码的测试向量,然后与未被切分的测试向量共同组成新的测试集,并将新测试集编码成线性反馈移位寄存器(LFSR)种子,从而实现测试数据压缩.该方法提高了LFSR的编码效率,取得了稍优于混合码的压缩率.与混合码复杂的解压结构相比,在硬件开销上具有明显的优势,仅需一个LFSR和简单的控制电路,且通信协议简单.     

一种多扫描链混合测试数据压缩方法

针对集成电路测试数据量大、测试应用时间长和测试结构复杂等问题,提出一种多扫描链的混合测试数据压缩方法。对于含无关位较多的测试向量,使用伪随机向量产生器生成。对于含无关位较少的向量,则直接使用自动测试设备存储。将该方法与另一种基于扫描阻塞的测试方法进行比较,理论分析和实验结果表明,该方法对数据的压缩效果优于单纯用伪随机方式的扫描阻塞测试方法。     

基于三态信号的改进游程编码压缩方法

为提高集成电路测试效率,提出一种结合三态信号的改进游程编码压缩方法.先对原始测试集进行部分输入精简处理并填充测试集的无关位,再对经过预处理的测试集根据游程长度进行变长分段处理找出最优段长.按照游程长度的出现频率对最优段长下的参考位设置编码表进行编码压缩,使用三态信号编码标志位并将编码压缩后的测试集存入自动测试设备(AT...     

Decompressors using nonlinear codes

Test patterns are usually transferred from the tester to the circuit under test in a compressed form as it minimizes test access mechanism bandwidth and transfer time. It was found that nonlinear binary codes could be used for encoding test patterns in a similar way as it is done using linear codes, and the compression efficiency may be higher. The key important characteristic of the nonlinear codes is that the maximum number of codeword bits may be higher than it is obtained for the linear code words while the number of individually specified bits is preserved. It causes better encoding parameters that can be found for the transformation of code words into a test pattern that can feed a circuit under test with a higher number of parallel scan chains. The decompressors placed on a circuit under test transform nonlinear binary code words into test patterns with the help of nonlinear combinational or sequential circuits. In this paper, we propose a relatively fast heuristics that can be used for finding the decompressor nonlinear function truth tables guaranteeing a required number of specified bits within a test pattern. We quantify the benefits and costs of such nonlinear decompressors and verify the benchmark circuit test pattern encoding efficiency.     

使用双重种子压缩的混合模式自测试

提出了一种基于扫描混合模式的内建自测试的新颖结构，为了减少确定测试模式的存储需求，它依赖一个双重种子压缩方案，采用编码折叠计数器种子作为一个LFSR种子，压缩确定测试立方体的个数以及它的宽度．这种建议的内建自测试结构是完全相容于标准的扫描设计，简单而具有柔性，并且多个逻辑芯核可以共享．实验结果表明，这种建议的方案比先前所公布方法需要更少的测试数据存储，并且具有相同的柔性和扫描相容性。     

Historical Perspective on Scan Compression

The beginnings of the modern-day IC test trace back to the introduction of such fundamental concepts as scan, stuck-at faults, and the D-algorithm. Since then, several subsequent technologies have made significant improvements to the state of the art. Today, IC test has evolved into a multifaceted industry that supports innovation. Scan compression technology has proven to be a powerful antidote to this problem, as it has catalyzed reductions in test data volume and test application time of up to 100 times. This article sketches a brief history of test technology research, tracking the evolution of compression technology that has led to the success of scan compression. It is not our intent to identify specific inventors on a finegrained timeline. Instead, we present the important concepts at a high level, on a coarse timeline. Starting in 1998 and continuing to the present, numerous scan-compression-related inventions have had a major impact on the test landscape. However, this article also is not a survey of the various scan compression methods. Rather, we focus on the evolution of the types of constructs used to create breakthrough solutions.     

A scheme of test data compression based on coding of even bits marking and selective output inversion

A new scheme of test data compression/decompression, namely coding of even bits marking and selective output inversion, is presented. It first uses a special kind of codewords, odd bits of which are used to represent the length of runs and even bits of which are used to represent whether the codewords finish. The characteristic of the codewords make the structure of decompressor simple. It then introduces a structure of selective output inversion to increase the probability of 0s. This scheme can obtain a better compression ratio than some already known schemes, but it only needs a very low hardware overhead. The performance of the scheme is experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.     

用扫描链重构来提高EFDR编码的测试压缩率和降低测试功耗

为了解决系统芯片测试中日益增长的测试数据和测试功耗的问题,提出一种不影响芯片正常逻辑功能的扫描链重构算法--Run-Reduced-Reconfiguration(3R).该算法针对扩展频率导向游程(EFDR)编码来重排序扫描链和调整扫描单元极性,重新组织测试数据,减少了游程的数量.从而大人提高了EFDR编码的测试压缩率并降低测试功耗;分析了扫描链调整对布线长度带来的影响后,给出了权衡压缩率和布线长度的解决方案.在ISCAS89基准电路上的实验结果表明,使用3R算法后,测试压缩率提高了52%,测试移位功耗降低了53%.     

一种针对传输小变化数据的位压缩算法

针对小变化量数据的传输提出一种转置矩阵位压缩算法,将变化位和非变化位清晰地分开,并对变化位以位为单位进行压缩。实验结果表明:该算法的对小变化量数据的压缩效果很好,即使使用极为简单的行程编码压缩算法也可以取得极高的压缩率;该算法用于处理类似于工业控制系统状态参数等数据时,可缓解系统的网络负荷压力,提高网络的传输效率。     

Test data compression based on geometric shapes

The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and efficient test-independent compression technique based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The test set is partitioned into blocks and then each block is encoded separately. The encoder has the choice of encoding either the 0’s or the 1’s in a block. In addition, it encodes a block that contains only 0’s (or 1’s) and x’s with only 3 bits. Furthermore, if the cost of encoding a block using geometric shapes is higher than the original cost of the block, the block is stored as is without encoding. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest full-scanned versions of ISCAS89 benchmark circuits. The proposed technique achieves significantly higher compression in comparison to other test-independent compression techniques reported in the literature.     

Machine learning based adaptive watermark decoding in view of anticipated attack

We present an innovative scheme of blindly extracting message bits when a watermarked image is distorted. In this scheme, we have exploited the capabilities of machine learning (ML) approaches for nonlinearly classifying the embedded bits. The proposed technique adaptively modifies the decoding strategy in view of the anticipated attack. The extraction of bits is considered as a binary classification problem. Conventionally, a hard decoder is used with the assumption that the underlying distribution of the discrete cosine transform coefficients do not change appreciably. However, in case of attacks related to real world applications of watermarking, such as JPEG compression in case of shared medical image warehouses, these coefficients are heavily altered. The sufficient statistics corresponding to the maximum likelihood based decoding process, which are considered as features in the proposed scheme, overlap at the receiving end, and a simple hard decoder fails to classify them properly. In contrast, our proposed ML decoding model has attained highest accuracy on the test data. Experimental results show that through its training phase, our proposed decoding scheme is able to cope with the alterations in features introduced by a new attack. Consequently, it achieves promising improvement in terms of bit correct ratio in comparison to the existing decoding scheme.     

基于Haar小波的自适应数据压缩方法

在无线传感器网络中,传感器节点的通信带宽有限,节点输出数据量需要与之匹配。针对该问题,设计高频系数选择算法确定待传输的Haar小波系数选择、量化和编码,通过自适应调整数据压缩率控制输出数据量。理论分析与仿真结果表明,该方法可充分利用节点通信带宽,当温度和湿度数据压缩率为0.9时,数据重构均方差小于0.1。     

无理数字典码的测试数据压缩方案

提出了一种无理数字典码的测试数据压缩方案,能有效地压缩芯片测试数据。方案利用无理数序列建立字典,编码时只需进行相容性检查,无需填充无关位,简化了操作步骤;同时,选择局部压缩率最大的一组数据作为最终编码结果,保证压缩效果可以达到局部最优。对ISCAS 89标准电路Mintest集的实验结果显示,该方案的压缩效果优于传统压缩方法,如Golomb码、FDR码、混合定变长码等。