On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.     

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.     

Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier Layers

The effect of SiN surface passivation by catalytic chemical vapor deposition (Cat-CVD) on Al/sub 0.4/Ga/sub 0.6/N-GaN heterostructure field-effect transistors (HFETs) was investigated. The channel sheet resistance was reduced by the passivation due to an increase in electron density, and the device characteristics of the thin-barrier HFETs were significantly improved by the reduction of source and drain resistances. The AlGaN(8 nm)-AlN(1.3 nm)-GaN HFET device with a source/drain distance of 3 /spl mu/m and a gate length of 1 /spl mu/m had a maximum drain current density of 0.83 A/mm at a gate bias of +1.5 V and an extrinsic maximum transconductance of 403 mS/mm. These results indicate the substantial potential of Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier layers.     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

Performance of the AlGaN HEMT structure with a gate extension

The microwave performance of AlGaN/GaN HEMTs at large drain bias is reported. The device structures were grown by organometallic vapor phase epitaxy on SiC substrates with a channel sheet resistance less than 280 ohms/square. The breakdown voltage of the HEMT was improved by the composite gate structure consisting of a 0.35 /spl mu/m long silicon nitride window with a 0.18 /spl mu/m long metal overhang on either side. This produced an metal-insulator-semiconductor (MIS) gate extension toward the drain with the insulator, silicon nitride, approximately 40-nm-thick. Transistors with a 150 /spl mu/m total gate width have demonstrated a continuous wave (CW) 10 GHz output power density and power added efficiency of 16.5 W/mm and 47%, respectively when operated at 60 V drain bias. Small-signal measurements yielded an f/sub T/ and f/sub max/ of 25.7 GHz and 48.8 GHz respectively. Maximum drain current was 1.3 A/mm at +4 V on the gate, with a knee voltage of /spl sim/5 V. This brief demonstrates that AlGaN/GaN HEMTs with an optimized gate structure can extend the device operation to higher drain biases yielding higher power levels and efficiencies than have previously been observed.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 /spl mu/m

In this letter, we report the effects of gate notching on the performance characteristics of short-channel NMOS transistor with the gate oxide thickness of 32 /spl Aring/. The significant gate-notching defect into channel region brings about the serious degradation of such transistor performances as transconductance (G/sub m/) characteristic and subthreshold swing (S/sub t/), resulting in increases of threshold voltage (V/sub TH/) and leakage current (I/sub OFF/) and the considerable reduction of drive current (I/sub ON/). We will suggest the local thickening of gate oxide as a main mechanism of its effects and show that lack of gate-to-source/drain extension (SDE) overlap may be an additional reason for the degradation of I/sub ON/ with increasing the notch depth.     

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.     

Passivation of interface-states in large-area Si devices using hydrogen implantation

We have found that in the large-scale transistor structures, where gate oxide thickness of 6 nm and below is used, the standard post-metallization (forming gas) annealing leaves a large number of Si/SiO/sub 2/ interface states unpassivated, with a lower limit of N/sub it/=5e11 cm/sup -2/. This may be due to the limited range of hydrogen (H) diffusion through the thin gate oxide and its ensuing inability to reach beyond the edges of the devices with a channel length larger than 3.0 /spl mu/m. In this study, we have shown that hydrogen ion implantation can successfully remove the residual interface state by placing the hydrogen uniformly throughout the area of a large device. Remarkable improvements in all the device characteristics, including capacitance and current versus voltage and the transistor threshold behavior as a function of the channel length, was achieved by hydrogen implantation and anneal as a final processing step.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

Ultranarrow and ideal rectangular cross section silicon(Si)-Fin channel double-gate MOSFETs (FXMOSFETs) have successfully been fabricated for the first time using [110]-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The transconductance (g/sub m/) normalized by 2/spl times/(Fin height) is found to be as high as 700 /spl mu/S//spl mu/m at V/sub d/=1 V in the fabricated 13-nm-thick and 82-nm-high Si- Fin channel double-gate MOSFET with a 105-nm gate length and a 2.2-nm gate oxide. The almost-ideal S-slope of 64 mV/decade is demonstrated in a 145-nm gate length device. These excellent results show that the Si-Fin channel with smooth [111]-oriented sidewalls is suitable to realize a high-performance FXMOSFET. The short-channel effects (SCEs) are effectively suppressed by reducing the Si-Fin thickness to 23 nm or less.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

AlGaN/GaN MIS-HFETs with f/sub T/ of 163 GHz using cat-CVD SiN gate-insulating and passivation Layers

Al/sub 0.4/Ga/sub 0.6/N/GaN heterostructure field-effect transistors (HFETs) with an AlGaN barrier thickness of 8 nm and a gate length (L/sub G/) of 0.06-0.2 /spl mu/m were fabricated on a sapphire substrate. We employed two novel techniques, which were thin, high-Al-composition AlGaN barrier layers and SiN gate-insulating, passivation layers formed by catalytic chemical vapor deposition, to enhance high-frequency device characteristics by suppressing the short channel effect. The HFETs with L/sub G/=0.06-0.2 /spl mu/m had a maximum drain current density of 1.17-1.24 A/mm at a gate bias of +1.0 V and a peak extrinsic transconductance of 305-417 mS/mm. The current-gain cutoff frequency (f/sub T/) was 163 GHz, which is the highest value to have been reported for GaN HFETs. The maximum oscillation frequency (f/sub max/) was also high, and its value derived from the maximum stable gain or unilateral gain was 192 or 163 GHz, respectively.     

A 150 ns, 150 mW, 64K dynamic MOS RAM

A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns.