一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

Integration of resonant-tunneling transistors and hot-electrontransistors

We have integrated a tunneling hot-electron transfer amplifier (THETA) and a novel resonant-tunneling hot-electron transfer amplifier (RTHETA) within a single epitaxial growth. At room temperature, the THETA exhibits a common-emitter current gain of greater than six and a voltage swing of 800 mV when measured in an inverter configuration. The RTHETA exhibits similar common-emitter current gain and a four-state voltage transfer characteristic with an output voltage swing of 1 V. In contrast to the resonant-tunneling hot-electron transistor (RHET), the RTHETA exhibits current gain both before and after the resonant peak voltage. From on-wafer S-parameter measurements, the current-gain cut-off frequency (f_T) and the maximum frequency of oscillation f_max) for both transistors are approximately 20 GHz and 9 GHz, respectively     

Temperature stabilized transistor amplifiers

A design procedure is evolved based on emitter-base voltage V/SUB EB/ and collector-base voltage V/SUB CB/ as stability parameters with the aim of achieving a gain stabilized transistor amplifier against temperature variations. Silicon transistors have been operated with a fairly stabilized gain in the temperature range from -15/spl deg/ to 270/spl deg/C. The voltage and power gains of this amplifier are found to be reasonably stable against unit to unit replacements. The circuits designed according to this approach are particularly suited for operation of long duration at elevated temperatures. The role of the leakage currents in affecting the operation of a several hour duration at elevated temperatures is investigated experimentally and it is found that the low I/SUB CB0/ units are better suited for such an operation. Further experimentations include the study of the gain stability characteristics of the amplifiers using Darlington pairs, CE-CE tandem connections, two stage RC-coupled amplifier, and the different amplifier.     

Cause of instability of power amplifier with parallel-connected power transistors

Power amplifiers with parallel-connected power transistors tend to be less stable than similar ones which use only one power transistor. Some designers believe that the reduced stability results from the larger collector-base capacitance C/SUB cb/ of the paralleled transistors making a larger degree of output-input feedback or making a larger nonlinear C/SUB cb/, thereby increasing the tendency toward parametric oscillation. Neither of these views is correct, as is shown here. The increased tendency toward oscillation results from the creation of additional modes of possible oscillation; these do not exist in the amplifier, which has only one transistor in a given stage of the amplifier. A preferred method is shown of connecting transistors in parallel, to minimize inequality of sharing input drive and output load and to minimize the tendency toward some modes of oscillation.     

Improved Schottky clamped (T/SUP 2/L) circuits

Al-Si Schottky clamped transistors used as fast switching signal devices or in integrated circuits are superior to gold-doped transistors for such parameters as low-level current gain, leakage current I/SUB CO/, and propagation delay t/SUB pd/. A digital application is used to show how some of these parameters can be optimized for a T/SUP 2/L circuit, providing high switching speed (t/SUB pd/ 4 to 5 ns) and a 40-percent better worst-case low-level noise margin than the usual gold-doped T/SUP 2/L circuit.     

A high precision component-tolerant A/D convertor

A pulse transformer is used to double and sum voltages in an A/D encoder that is based on the recursive algorithm V/SUB i+1/=V/SUB REF/-s|V/SUB i/|. As a result of isolating the transformer from the input signal d.c. component, independence of circuit zero drift is achieved. Resistor and V/SUB BE/ mismatch do not affect the encoder accuracy. Automatic zero and gain correction are employed to provide stable adjustment-free operation. A custom analog processor chip carrying both MOS and bipolar transistors was fabricated to implement the algorithm. The 12-bit resolution with a maximum encoder error of 250 /spl mu/V in a temperature range from 0-70/spl deg/C was achieved at 20-kHz sampling rate.     

An analysis of low-frequency second-order distortion in bipolar transistors applied to an amplifier

A distortion theory for bipolar transistors is applied to reduce low-frequency second-order distortion M/SUB 2/ in an amplifier. An equation for M/SUB 2/ is developed in terms of the physical parameters of the transistor. It is found that M/SUB 2/ depends critically on generator resistance that can be optimized for the transistor studied. The theory and this finding are then applied to the distortion producing Darlington pair in an amplifier, and an optimal value of base resistance for the second transistor is predicted and verified to improve M/SUB 2/ by 30 dB at 5 MHz for the pair. The corresponding improvement in the amplifier is 17 dB (from -50 to -70 dB) at 5 MHz and is accompanied by a small, acceptable degradation in M/SUB 3/ of 3 dB at high frequencies.     

An AlGaAs/GaAs heterostructure-emitter bipolar transistor

An AlGaAs/GaAs heterostructure-emitter bipolar transistor using separate carrier injection and confinement is discussed. A common-emitter current gain of 28 with BV_CEO=15 V was obtained at a base doping level of 1×10¹⁹/cm³ . No spacer layer was inserted in the structure. This transistor combines the merits of homojunction transistors and regular heterostructure bipolar transistors (HBTs) and is simple to fabricate     

A curve-fitted circuits model for bipolar transistor f/SUB T/ roll-off at high injection levels

This paper introduces a simple empirical relationship for modelling the common-emitter short-circuit gain-bandwidth product (f/SUB T/) of bipolar transistors operated in high-injection regimes. The model simulates the dependence of f/SUB T/ on both collector current and collector voltage to within an error of no more than 20 percent.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Power feedthrough via C/SUB cb/ in common-emitter class C RF power amplifiers-a commonly believed fallacy

It is suggested that the assumption that the direction of power flow through C/SUB cb/ of the transistor is necessarily from the input-drive source to the amplifier output is a fallacy. Depending on the collector circuit tuning, RF power may be fed to the drive source from the amplifier, or vice versa, or zero RF power may be exchanged through C/SUB cb/. The importance of a correct understanding of this subject is emphasized. It can guide the engineer in designing amplifiers which have higher power gain, higher collector efficiency, more margin of stability against oscillation, and which function properly by design instead of by luck. Circuit operation is explained with reference to experimental voltage and current waveforms.     

Intermodulation distortion of a bipolar common-emitter amplifier with arbitrary emitter impedance and input matching network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.     

Fabrication of widegap-emitter Schottky-collector transistor using GaInAs/InP

A widegap-emitter transistor with a Schottky collector has been fabricated using n-InP as the emitter, p-GaInAs as the base layer and Ni as the Schottky metallisation. The fabricated transistors show a current gain better than 5 in the common-emitter configuration.     

High-efficiency Ku-band HBT MMIC power amplifier

A Ku-band monolithic HBT power amplifier was developed using a metal-organic chemical vapor deposition (MOCVD)-grown AlGaAs/GaAs heterojunction bipolar transistor (HBT) operating in common-emitter mode. At a 7.5 V collector bias, the amplifier produced 0.5 W CW output power with 5.0 dB gain and 42% power-added efficiency in the 15-16 GHz band. When operated at a single frequency (15 GHz), 0.66 W CW output power and 5.2 dB of gain were achieved with 43% PAE     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

The relevance of fT and fmax for the speed ofa bipolar CE amplifier stage

Expressions relating the bandwidth of a common-emitter (CE) amplifier stage and the small-signal CML gate delay time to directly measurable transistor parameters, such as f_T, f_max, and input bandwidth f_υ, are presented. They are valid for an arbitrary division of the base resistance and base-collector depletion capacitance into internal and external components. No resistance measurements are needed. It is shown that the transistor input bandwidth f_υ is an important figure of merit for the speed of a CE stage. Under a given bias condition, f_υ is determined by the base resistance and the cut-off frequency. In most cases the value of the maximum oscillation frequency f_max is only of minor importance. It would therefore be more meaningful to present besides f_T also f_υ instead of f_max as a figure of merit for transistors for high-speed, low-power analog and digital circuits     

Design analysis of a gain-stabilized transistor amplifier at elevated temperatures using passive elements

The decrease of the emitter-base and collector-base junction voltages of a transistor with temperature and the effect of the external circuit resistances on these voltages are studied theoretically and experimentally. The influence of the shifting of the operating point with temperature on the gain is discussed. A new design approach based on V/SUB EB/ and V/SUB CB/ as the stability parameters is given using only passive components. It is found that this approach definitely leads to better gain stability with temperature than other design techniques using NTC elements. Although work in the early stages was concentrated on germanium transistors (-15 to +115/spl deg/C), already some encouraging results have also been attained in the study of silicon transistors.     

Inductor simulation using a single unity gain amplifier

A circuit consisting of a single unity gain amplifier, two resistors (R/SUB 1/,R/SUB 2/), and a capacitor (C) is presented for realization of a grounded inductor for integrated circuits. The circuit behaves as an inductor with inductance L=CR/SUB 1/R/SUB 2/ and maximum Q/SUB 0/=(R/SUB 1//R/SUB 2/)/SUP 1/2//2. Experimental results agree closely with the theoretical calculations.     

程控增益低噪声宽带直流放大器的设计

介绍了程控增益低噪声宽带直流放大器的设计原理及流程。采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了程控增益低噪声宽带直流放大器,实现了输入电压有效值小于10mV,输出信号有效值最大可达10V,通频带为0～8MHz,增益可在0～50dB之间5dB的步进进行控制,最高增益达到53dB,且宽带内增益起伏远小于1dB的两级宽带直流低噪声放大器的设计。     

Small-signal substrate resistance effect in RF CMOS cascode amplifier

With common-source RF application amplifier, it is well known that the small substrate resistance helps to improve the output resistance as well as the transconductance. This idea can be easily extended to all CMOS transistors in RF applications. However, with cascode amplifier at high frequencies, the maximum available gain, noise figure minimum, and the tuned output impedance are improved by increasing the substrate resistance of the common-gate transistor, so that the range of operational frequency can be extended. These contradicting phenomenons between the common-source and common-gate topology can be explained theoretically, and the supporting measurement results are presented base on a 0.35 /spl mu/m CMOS technology.