多束质子辐照晶闸管的退火研究

研究了多束质子辐照对晶闸管开关特性和通态电压的影响，分析了退火机理，找出了最佳退火流程，获得了优良的通态电压与关断时间（VTM－Tq）的折衷关系。     

Plasma etching of copper films at low temperature

Experimental verification of a low temperature (<20 °C), reactive plasma etch process for copper films is presented. The plasma etch process, proposed previously from a thermochemical analysis of the Cu-Cl-H system, is executed in two steps. In the first step, copper films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is volatilized as Cu₃Cl₃ by exposure to a H₂ plasma in the second step. Plasma etching of thin films (9 nm) and thicker films (400 nm) of copper has been performed; chemical composition of sample surfaces before and after etching has been determined by X-ray photoelectron and flame atomic absorption spectroscopies.     

Improvement in HgCdTe diode characteristics by low temperature post-implantation annealing

Hg_1−xCd_xTe diodes (x∼0.22) with different carrier concentrations in p type materials have been fabricated by employing an ion-implantation technique. The performances of the diodes, prior to and after low temperature postimplantation annealing, have been investigated in detail by model fitting, taking into account dark current mechanisms. Prior to the annealing process, dark currents for diodes with relatively low carrier concentrations are found to be limited by generation-recombination current and trap-assisted tunneling current, while dark currents for diodes with higher carrier concentrations are limited by band-to-band tunneling current. These dark currents in both diodes have been dramatically decreased by the low temperature annealing at 120∼150°C. From the model fitting analyses, it turned out that trap density and the density of the surface recombination center in the vicinity of the pn junction were reduced by one order of magnitude for a diode with lower carrier concentration and that the carrier concentration profile in a pn junction changed for a diode with higher carrier concentration. The improvements are explained by changes in both carrier concentration profile and pn junction position determined by interaction of interstitial Hg with Hg vacancy in the vicinity of the junction during the annealing process.     

低温退火对铁硅合金中立方织构形成的影响

利用光学显微镜、SEM、TEM和EBSD分析研究了Fe-3.2%Si合金在低温初次再结晶退火和较低温度下二次再结晶退火后立方织构的形成。结果表明：采用低温退火可以在初次再结晶组织中获得（100）[001]织构及（hk0）[001]织构,并且这种初次再结晶组织在较低的二次再结晶温度下可演化成比较集中的立方织构。     

Influence of annealing temperature on field emission from tetrapod-shaped ZnO-whisker films obtained by screen printing

Tetrapod-shaped zinc oxide whisker-film emitters were fabricated on indium tin oxide glass substrates using a screen-printing method. The influence of annealing temperature on field emission of tetrapod-whisker ZnO-based emitters was investigated. X-ray diffraction and scanning electronic microscopy were applied to characterize the structure and the surface morphology of the deposited films. It was found that ZnO-based emitters annealed at 250 °C have the best field emission properties with the lowest turn-on field of 2.6 V/μm at a current density of 1 μA/cm², the lowest threshold field of 5.2 V/μm at a current density of 1 mA/cm² and high field emission enhancement factor of 4129. Moreover, films with homogeneous, fine and dense light spots with low emission current fluctuation of 1.7% were obtained from samples annealed at 250 °C.     

高T_C低电阻率PTCR陶瓷材料

研究了在制备高ＴＣ低电阻率ＰＴＣＲ陶瓷材料过程中，原材料、少量添加物以及主要生产工艺对电性能的影响规律。经反复试产表明，在隧道窑可以大规模生产出居里点ＴＣ＝１８０～２７０℃、室温电阻率ρ２５＜８０Ω·ｃｍ、电阻温度系数α４０≈１４％℃－１、升阻比Ｒｍａｘ／Ｒｍｉｎ为１０４的高性能ＰＴＣＲ陶瓷材料。此种材料制成高温发热元件能在６～２４Ｖ电压下使用，开拓了ＰＴＣＲ材料新的应用领域。     

射频磁控溅射ITO薄膜中沉积温度对膜特性影响

采用射频磁控溅射的方法,在溅射过程中改变沉积温度以提高铟锡氧化物(ITO)薄膜的电学和光学特性。采用扫描电镜(SEM)分析了ITO薄膜的表面形貌,发现ITO薄膜的晶粒尺寸随着衬底温度的升高而增大。经过后续退火,ITO薄膜的电学特性得到了较大的提高。在溅射条件为工作气压1 Pa、衬底温度200℃和输入功率200 W沉积的样品经过300℃真空退火2 h获得了12.8×10-4Ω.cm的低电阻率和800 nm波段94%的高透过率。     

Ion-beam mixed ultra-thin cobalt suicide (CoSi2) films by cobalt sputtering and rapid thermal annealing

The influence of ion-beam mixing on ultra-thin cobalt silicide (CoSi₂) formation was investigated by characterizing the ion-beam mixed and unmixed CoSi₂ films. A Ge⁺ ion-implantation through the Co film prior to silicidation causes an interface mixing of the cobalt film with the silicon substrate and results in improved silicide-to-silicon interface roughness. Rapid thermal annealing was used to form Ge⁺ ion mixed and unmixed thin CoSi₂ layer from 10 nm sputter deposited Co film. The silicide films were characterized by secondary neutral mass spectroscopy, x-ray diffraction, tunneling electron microscopy (TEM), Rutherford backscattering, and sheet resistance measurements. The experi-mental results indicate that the final rapid thermal annealing temperature should not exceed 800°C for thin (<50 nm) CoSi₂ preparation. A comparison of the plan-view and cross-section TEM micrographs of the ion-beam mixed and unmixed CoSi₂ films reveals that Ge⁺ ion mixing (45 keV, 1 × 10¹⁵ cm⁻²) produces homogeneous silicide with smooth silicide-to-silicon interface.     

Defects annealing in 4H–SiC epitaxial layer probed by low temperature photoluminescence

The thermal evolution of defects induced in 4H–SiC by multiple implantation of C ions was investigated by Low Temperature Photoluminescence in the temperature range 450–1000 K. The photoluminescence spectra show sharp luminescent lines (alphabet lines) in the wavelength range 426–440 nm upon irradiation and thermal treatment at 450 K induces the appearance of a new line at 427 nm (D_I centre). The trend shown by the luminescence lines as a function of the temperature is quite complex. The alphabet lines intensity increases up to 850 K, whereas at higher temperature decreases with an activation energy of 2.0 eV, suggesting that the defect, responsible for these lines, is the Si-vacancy. The luminescence yield of D_I centre is always increasing as a function of the temperature, with a higher slope from 750 K, suggesting a correlation to the reconfiguration and to the annealing of point defects.     

退火温度对Cr-Si压阻薄膜电性能的影响

采用射频磁控溅射法在氧化铝陶瓷基底上制备了Cr-Si-Ni-Ti压阻薄膜,研究了不同退火温度对薄膜电性能的影响.结果表明:在溅射态及退火温度低于600℃时,薄膜为非晶态.随着退火温度的升高,薄膜的电阻温度系数(TCR)逐渐增大,应变因子(GF)先增大后减小,室温电阻率(ρ)则逐渐降低.在退火温度为300℃时,Cr-Si...     

高温退火对MgO晶体光致发光性能的影响

利用自行搭建的实验平台,测试了高纯MgO晶体和Sc掺杂MgO晶体的紫外光光致发光(PL)光谱,发射峰值分别位于389.31、498.61nm、712.44和749.06nm,其可见光发射区和红外发射区主要对应于MgO晶体中由O空位构成的F色心和F+色心通过激发和退激发机制发射;在不同温度退火条件下测试Sc掺杂MgO晶体的PL光谱,并利用高斯分解实现了Sc掺杂MgO晶体中F色心和F+色心的定位。结果表明,高温退火处理可以有效降低MgO晶体表面的污染,进而提高晶体的光电活性;Sc掺杂导致MgO晶体可见光发射区域的蓝移和增强,其中F+色心对于温度的依赖性较强。     

扁平化及退火温度对FeSiAl合金吸波性能的影响

采用湿磨工艺对水雾化FeSiAl粉末进行了扁平化,然后在不同温度下对其进行了退火处理。借助XRD,SEM和VSM,研究了扁平化工艺和退火温度对FeSiAl粉末物相组成、形貌和静磁性能的影响。另外,借助矢量网络分析仪,考察了以所制合金粉末为吸收剂制成的吸波材料在0.5~4.0 GHz频率范围内的电磁参数与吸波性能。结果表明:经扁平化和退火处理后,FeSiAl吸波材料的复磁导率得到了显著提高。与由未经处理的FeSiAl粉末制成的吸波材料相比,由经扁平化并经700℃退火的FeSiAl粉末制成的吸波材料在0.5~4.0 GHz的低频段具有更加优异的吸波性能。     

低温固化银系导电油墨导电性能的影响因素

为了提高低温固化银系导电油墨的导电性,对导电机理进行了研究。通过实验研究了聚合物分子结构,银粉的含量、形貌、粒径,溶剂种类对导电性能的影响。得出:氯化聚乙酸乙烯为主体树脂,以片状与球状混合银粉(质量比为9:1)为导电填料,并以酮和酯组成混合溶剂,调制的导电油墨导电性最好,其Rs达9 mΩ/□。     

高倍增低暗电流的AlInAsSb四元数字合金雪崩光电二极管

用分子束外延系统（MBE）生长高质量GaSb基AlInAsSb四元数字合金制作雪崩光电二极管（APD）。为了克服随机体材料生长方式发生的偏析现象,采用迁移增强的数字合金生长方式,其快门顺序为AlSb,AlAs,AlSb,Sb,In,InAs,In,Sb。其高分辨率X射线衍射（HRXRD）曲线显示出尖锐的卫星峰,并显示出几乎完美的晶格匹配,其原子力显微镜（AFM）图像上也可以观察到光滑的表面形貌。使用优化的数字合金生长方式,制备了分离吸收、渐变、电荷和倍增（SAGCM）型的AlInAsSb数字合金APD。在室温下,器件在95%击穿时,暗电流密度为0.95 mA/cm²,击穿前最大稳定增益高达~100,其器件的高性能显示出光电领域进一步发展的潜力。     

AIN／SiO2-B2O3-ZnO-Bi2O3低温共烧玻璃陶瓷

制备了SiO2-B2O3-ZnO-Bi2O3系玻璃,并且与AlN液相烧结得到低温共烧玻璃陶瓷.分析了样品的相结构、形貌、介电常数、介质损耗、热导率和热膨胀系数等性能.结果表明AlN与SiO2-B2O3-ZnO-Bi2O3系玻璃在950℃能够很好地烧结.该陶瓷的性能取决于烧结体的致密度和玻璃含量,当w(玻璃)为40%～60%时,陶瓷具有较低的εr(3.5～4.8)和tan δ[(0.13～0.48)×10-2]、较高的λ[5.1～9.3 W/(m·K)]以及与Si相接近的αl(2.6～2.8)×1-6·K-1],适用于低温共烧基板材料.     

Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

Uniformity of deep levels in semi-insulating InP obtained by multiple-step wafer annealing

The uniformity of deep levels in semi-insulating InP wafers, which have been obtained by multiple-step wafer annealing under phosphorus vapor pressure, was studied using the thermally stimulated current (TSC) and photoluminescence (PL) methods. Only three traps related to Fe, T₀ (ionization energy E_i=0.19 eV), T₁ (0.25 eV), and T₂ (0.33 eV), probably forming complex defects, were observed in the wafer and they exhibited a relatively uniform distribution. PL spectra relating to phosphorus vacancies observed in some regions of the wafer are correlated with a small TSC signal having an ionization energy of 0.43 eV.     

Optical and electrical measurement of FeSe2 thin films obtained at low temperature

FeSe₂ thin films were prepared at low temperature by thermal annealing at 350 °C during 6 h of sequentially evaporated iron and selenium films under selenium atmosphere. The structural, optical and electrical characteristics were investigated. The roughness of films (~76 nm) was confirmed by AFM images. Moreover, optical band gap of FeSe₂, which was evaluated as nearly 1.11 eV and confirmed by the electrical study which yielded a value in the order of 1.08 eV. The electrical conductivity, conduction mechanism, dielectric properties and relaxation model of theses thin films were studied using impedance spectroscopy technique in the frequency range 5 Hz–13 MHz under various temperatures (180–300 °C). Besides, complex impedance and AC conductivity have been investigated on the basis of frequency and temperature dependence.     

Effects of prolonged annealing on NiSi at low temperature (500°C)

The effects of prolonged annealing (10 h) at low temperature (500°C) have been studied in 20-nm Ni/Si (100) thin films using Rutherford backscattering spectroscopy (RBS), x-ray diffraction (XRD), scanning electron microscopy (SEM) in conjunction with energy-dispersive spectrometry (EDS), and four-point probe techniques. We observe that nickel monosilicide (NiSi) is stable up to 4 h annealing at 500°C. It is also found that, after 6 h and 10 h annealing, severe agglomeration sets in and NiSi thin films tear off and separate into different clusters of regions of NiSi and Si on the surface. Due to this severe agglomeration and tearing off of the NiSi films, sheet resistance is increased by a factor of 2 despite the fact that no NiSi to NiSi₂ transition occurs. It is also observed that, with increasing annealing time, the interface between NiSi and Si becomes rougher.     

Inkjet printable and low annealing temperature gate-dielectric based on polymethylsilsesquioxane for flexible n-channel OFETs

We report on inkjet printable gate-dielectric based on a spin-on-glass (SOG) material for applications in n-type organic field-effect transistors (OFETs). The SOG material is polymethylsilsesquioxane in alcohol mixture. After annealed at 135 °C in air, the SOG films are well crosslinked and have a good resistance against alcohol, which allows for the inkjet printing of Ag gate electrodes on top of the SOG dielectric. The crosslinked SOG films are very dense, and can withstand high electric field. This is very beneficial to the operation of transistors. In addition, the SOG films have very low hydroxyl content after annealing. This property is very important for n-type transistors. After ink formulation, this SOG dielectric has an excellent inkjet-ability with good uniformity and reproducibility. By using Polyera's P(NDI2OD-T2) as the semiconductor and SOG as the dielectric, bottom-contact top-gated n-type transistors were successfully fabricated on PET substrates with electron mobility above 0.1 cm²/V and high on/off ratio well above 10⁵. These remarkable results demonstrate that this newly formulated SOG dielectric is a promising candidate for the future development of flexible electronic devices.