一种ISM 2.4GHz的低功耗低中频射频接收机前端

本文描述了一种工作在2.4GHz ISM频段的低功耗、低中频射频接收机前端电路,使用TSMC 0.13um CMOS工艺。整个前端包括一个低噪声放大器以及两次变频下变换混频器。低噪声放大器通过在输入级引入额外的栅-源电容实现了低功耗与低噪声的设计;在下变换混频器设计中,分别使用一个单平衡射频混频器以及两个双平衡低中频混频器实现两次变频下变换技术;射频混频器输入晶体管源极串联电感-电容谐振网络以及低噪声放大器输出级的电感-电容谐振网络总共实现了30dB的镜像抑制率。整个前端占用芯片面积约0.42mm2,在1.2V的供电电压下,仅耗功率4.5mW,实现了4dB的噪声系数,在高增益模式下,获得-22dBm的三阶交调线性度,整个链路电压增益为37dB。     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

A dual-band direct-conversion RF front-end for WiMedia UWB receiver

This paper describes a direct-conversion RF front-end designed for a dual-band WiMedia UWB receiver. The front-end operates in band group BG1 and BG3 frequencies. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. The UWB receiver is targeted for a mobile handset, where several other radios can be simultaneously on. Therefore, special attention was paid on minimizing the interference from different wireless systems. The front-end achieves approximately 26-dB gain and 4.9–5.6-dB noise figure (NF) across three sub-bands of BG1. In BG3 mode it obtains 23–26-dB gain and 6.9–7.7-dB NF. The front-end consumes 48.1 and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-μm CMOS.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A 1.57-GHz RF front-end for triple conversion GPS receiver

A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 μm BiCMOS technology. It consists of a low noise amplifier with 15 dB of gain, a single balanced mixer with 6.3 mS of conversion g_m, a Colpitts LC local oscillator, and an emitter coupled logic (ECL) divide-by-eight prescaler. This front-end has a single sideband (SSB) noise figure of 8.1 dB and is part of a triple conversion superheterodyne receiver whose IF frequencies are 179, 4.7, and 1.05 MHz. Low power consumption has been achieved, with 10.5 mA at 3 V supply voltage for the front-end, while the complete receiver is expected to draw about 12 mA     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

用于315/433MHz超再生接收机的射频前端关键技术

采用0.5μm CMOS工艺实现了用于315/433MHz超再生无线接收机的射频前端电路,包括射频放大器和超再生振荡器。文中提出了一种改进型有源电感,提高了射频放大器中谐振回路的品质因数。阐述了振荡器的自偏置效应以及振荡器输出信号幅度和电流源的关系,在此基础上实现了适用于包络检波的差分结构超再生振荡器。测试结果显示,电源电压范围为2.5V~5V,电流小于2.5mA,系统接收灵敏度优于-90dBm。     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

差分式低电压高增益电流模式集成射频接收机前端

本文提出了一种用于802.11 b 无线局域网的差分式低电压该增益电流模式射频前端集成电路。该电路包含一个差分式跨导低噪声放大器和一个差分式电流模式下混频器。单边跨导低噪声放大器仅含一个MOS晶体管和2个电感、2个电容构成。放大器中的栅-源并联电容Cx1 和 Cx2 不仅能减小栅-源寄生电容对谐振频率和输入匹配阻抗的的影响,而且能使得栅电感的取值变小。电流模式混频器由开关电流镜构成。调节开关电流镜晶体管之间沟道尺寸比值可以增加混频器的增益,从而增大射频接收机前端的功率增益。该射频前端电路工作在1V的电源电压下。使用chartered 0.18μm CMOS工艺进行了流片。 对芯片进行测试得到该射频前端的功率增益为17.48 dB, 输入三阶交调截点 (IIP3) 为 -7.02 dBm. 后仿真表示该芯片的噪声系数为4.5 dB,功耗仅为 14mW。     

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed.It contains a differential transconductance low noise amplifier（G_m-LNA） and a differential current-mode 0 down converted mixer.The single terminal of the G_m-LNA contains just one MOS transistor,two capacitors and two inductors.The gate-source shunt capacitors,C_x1 and C_x2,can not only reduce the effects of gate-source C_gs on resonance frequency and input-matching impedance,but they also enable the gate inductance L_g1,2 to be selected at a very small value.The current-mode mixer is composed of four switched current mirrors.Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end.The RF front-end operates under 1 V supply voltage.The receiver RFIC was fabricated using a chartered 0.18μm CMOS process.The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point（IIP3） of-7.02 dBm.The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.