Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced     

High speed electron-beam testing of VLSI circuits by backscattered electron detection

A scheme which is predicted to increase the time resolution of electron beam testers by more than an order of magnitude to a value of around 400 fs is described. The new proposal is based on using multi-channel angular backscattered detection which can be used in conjunction with the normal operating mode of electron beam testers.<>     

Applications of VLSI circuits to medical imaging

The application of advanced VLSI circuits to medical imaging is explored. The relationship of both general-purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced-aided design tools for silicon compilation are presented. Particular attention is given to the application of VLSI circuits to 3-D image display with ultrasound systems. It is concluded that devices built with these tools represents a possible alternative to custom devices and general-purpose signal processors for the next generation of medical imaging systems     

Hybrid evolutionary partitioning algorithm for heat transfer enhancement in VLSI circuits

In this paper, a new approach to improving the heat transfer in integrated circuits (ICs) is presented. It is based on improving the thermal conductivity of ICs by increasing the number of their external connections up to the level determined by the packaging standard. In order to attain this goal, a new hybrid evolutionary partitioning algorithm (HEPA) for circuits partitioning is introduced. The computations carried out for the chosen benchmarks show that HEPA is able to reach optimal solutions in the case of bipartitioning problem, and almost optimal in the case of k-way partitioning (k>2). The presented approach is especially dedicated for a flip chip interconnect technology which is used in contemporary ICs.     

Electron beam testing of VLSI circuits assisted by focused ion beam etching

Electron beam testing assisted by focused ion beam etching was examined. Before electron beam testing (EB testing), a small window was made in the passivation film by focused ion beam etching (FIB etching). EB testing was performed through this window. This method was useful because charge buildup on the passivation film is avoided during EB testing. The threshold voltage shift caused by FIB etching was permitted until the residual film thickness on the gate electrode became 0.5μm. This technique was applied to measure the internal voltage waveform of the 256K bit dynamic RAM and confirmed that it was effective for functional testing and failure analysis of VLSI circuits.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Power-supply current diagnosis of VLSI circuits

This paper presents a technique based upon the power supply current signature (PSCS) which allows testing of mixed-signal systems, in situ. The PSCS contains important information concerning the operational status of the system; such information can be extracted using approaches based on statistical signal detection theory. The fault-detection performance of these techniques is superior to that achieved through autoregressive modeling of the PSCS. These methods are suitable for production testing of cost-sensitive devices and field testing of mission-critical systems     

High-speed parallel CRC circuits in VLSI

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.     

Noise spikes in digital VLSI circuits

An analysis is presented of the appearance of occasional noise spikes in very complex VLSI circuits. The noise spikes may cause so-called soft errors if the operating frequency is high and the variations in channel resistance large. The main contributing noise source is capacitive and inductive crosstalk. Noise spikes in present-day circuits are about an order of magnitude smaller than spikes caused by radioactive decay of trace elements in the encapsulation, and by cosmic rays. Fault-tolerant circuit design reducing the influence of radioactive and cosmic ray bombardment will help against noise spikes as well. A comparison is made with noise spikes in neurons.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.     

High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Estimating power dissipation in VLSI circuits

With the shift to low power IC design for personal computing and communication applications, designers' priorities turn to accurate and efficient estimation of power consumption in ICs. Traditional current and power estimation techniques based on a SPICE-like simulation do not provide the necessary efficiency for such an application, and thus new approaches have been recently proposed. In this, the first of a series of articles that reflect the new orientation of this column, Professor Farid Najm of the University of Illinois at Urbana-Champaign presents an overview of different techniques for estimating power consumption in large-scale IC designs. He also discusses computer aided design tools to help in the task     

Ground bounce in digital VLSI circuits

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.     

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.     

Modelling noise and delay in VLSI circuits

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.