Identification and implication of a perimeter tunneling currentcomponent in advanced self-aligned bipolar transistors

The identification of a perimeter tunneling current in the base-emitter junction of advanced double-poly self-aligned bipolar transistors has been verified by measuring based current as a function of temperature, bias voltage, and device perimeter-to-area ratio. The perimeter tunneling current at forward bias is found to be predominantly an excess tunneling that depends on the sidewall oxide interface properties, while that at reverse bias is due to band-to-band tunneling resulting from the emitter and extrinsic base profile overlap. Based on experimental results and an analysis of base-leakage-current trade-offs at forward and reverse bias, a device design concept was developed to enhance device performance and processing yield in scaled bipolar transistors     

Double-interdigitated power transistors

The results of a comprehensive investigation concerning the implementation of the double-interdigitated (TIL) concept in TO-3-packaged triple-diffused power n-p-n^--n transistors are reported. The ease of manufacturing is accompanied by a relaxation of the tradeoff between the doping and width of the p-base and the main transistor parameters, which is still a crucial issue in conventionally interdigitated switches. The advantages exhibited by TIL devices when compared with identical conventional interdigitated transistors processed simultaneously are discussed     

Efficiency of gate control in double-interdigitated (TIL) GTO thyristors

The research reported in this work was focused on the efficiency of gate control during turn-off in the recently developed double-interdigitated (TIL) GTO thyristors. The 8 mm² area, TO-220 packaged, high voltage test devices were investigated under both current and voltage input conditions. The main monitored parameters were: the peak turn-off gain K_off(max), the components of the turn-off time and the gate pulse width t_gr. During the tests the TIL GTOs were driven up to an anode current i_T = 50 A, a value equal to the non-repetitive peak on-state current (I_TSM) of these thyristors.The performed investigations have shown that these novel GTO devices possess a good efficiency of gate control expressed by: 1) low power consumption by the gate under both current and voltage drive conditions; 2) extremely high turn-off gain K_off(max), which is an increasing function of the anode current in a wide range of gate signals amplitudes and durations; 3) fast turn-off of large amounts of anode current with relatively short gate pulse widths; 4) substantial reduction of the storage time t_s and fall time t_f through adequate current or voltage drive. Design/behavioral details are given, which are useful in the implementation of the TIL concept in GTOs and other power switching devices, such as the bipolar transistors.     

PWM Inverter Using High-Gain Pulse-Triggered Power Transistors and a New PWM Control Method

Rugged PWM transistor inverters are expected to be put into practical use for providing high reliability under adverse operating conditions. The bipolar power transistors are more common compared with MOSFET's power transistors in balance between power-handling capability and switching speed. High over current capability, low switching loss, high-speed switching, and high-current gain are requisite functions in the PWM inverter employing bipolar power transistors. These functions are of great concern in the power electronics field. A new PWM transistor inverter which can meet these requirements is presented in this paper. For this purpose, a concept of high-gain pulse-triggered power transistor (PTPT) with amorphous saturable current transformer (CT) is introduced.     

An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

Simulation and investigation of a bipolar transistor with transfer <Emphasis Type="Italic">N</Emphasis>-shaped current-voltage characteristic

The method of the implementation of built-in protection of bipolar transistors from the current overloads in the controlling circuit based on the combination of an element with an N-shaped IVC with the bipolar transistor is considered. The use of the given method makes it possible to create semiconductor structures of bipolar transistors with built-in protection against current overloads in the controlling circuit.     

Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

非晶硅发射区双极晶体管的低温特性

本文研究了非晶硅发射区双极晶体管的低温特性，得出了如下结论：低温下电流增益随基区杂质浓度的上升而下降，不同于常规同质结双极晶体管的情况，集电极电流则随基区杂质浓度的上升而上升。这些结果将为低温双极晶体管的设计提供理论依据。     

PMOS input merged bipolar/sidewall MOS transistors (PBiMOStransistors)

A concept of merging vertical n-p-n bipolar and sidewall PMOS transistors into merged PBiMOS transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy ~1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n^- collector of the n-p-n bipolar and the channel of the sidewall PMOS transistors are similar     

Enhanced current gain in SiC power BJTs using a novel surface accumulation layer transistor concept

In this paper, we demonstrate that the current gain of SiC power bipolar transistors can be improved by as large as 100% by using a novel surface accumulation layer transistor concept in which a reflecting boundary in the emitter reduces the base current. The reasons for the improved current gain are explained based on simulation results.     

低温、低频双极晶体管的噪声分析

建立了低温双极晶体管的低频噪声模型，对低温、低频双极晶体管的噪声进行了分析，并给出了噪声电压随工作温度、工作电流以及频率的三维变化曲线，指出了双极晶体管获得最小噪声的最佳工作温度和最佳工作电流。通过对低温双极晶体管的ＣＡＴ噪声测试，证明了我们的噪声分析结果。     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

A new method for determining the reverse transit time in bipolartransistors

The reverse transmit time is an important parameter for determining the delay of bipolar transistors in saturation. A new method is proposed to extract the reverse transit time of bipolar transistors. The technique is based on AC short-circuit current gain measurements using a network analyzer. The method is very simple and is very useful for on-wafer measurements     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

不同类型双极晶体管抗辐照性能的研究

时于制作工艺相同的NPN和LPNP两种类型的双极型晶体管进行了辐照实验,研究了不同类型双极晶体管的电离总剂量辐射损伤机理和退火效应。实验结果表明：在相同的辐照总剂量下．LPNP型双极晶体管的归一化电流增益的下降比NPN型双极晶体管的下降多．说明LPNP型双极晶体管的辐照敏感性更强。这与NPN和LPNP这两种类型的双极晶体管的辐射损伤机理的不同有关。对于NPN型双极晶体管,电离辐照总剂照效应主要是造成氧化物正电荷的积累：而对于LPNP型双极晶体管．电离辐照总剂量效应主要是造成界面态密度的增加。     

Performance limitations of silicon bipolar transistors

The author considers some performance limitations of silicon bipolar transistors, assuming our ability to fabricate small geometric devices, by device analysis using an accurate two-dimensional numerical solution of classic semiconductor transport equations. The applicability of mathematical equations used to represent carrier transport in small geometric bipolar transistors and silicon-material parameters, such as bandgap narrowing with doping, ionization coefficients, and lifetime, used in the model has also been considered. The terminal characteristics, the internal behaviour, and performance limitations due to voltage and current operating levels of bipolar transistors with emitter depths and basewidths ranging from 0.4 /spl mu/m to 30 nm have been analyzed.     

硅双极晶体管直流特性低温效应的研究

从理论和实验上研究了硅双极晶体管直流特性的低温效应,建立了不同发射结结深的硅双极晶体管电流增益的温度模型,讨论了不同工作电流下H_(FE)的温度特性,并分析了大电流下基区展宽效应的温度关系。     

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF₂ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G_b) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h_fe) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h_fe-V_A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h_fe≈1600, excellent collector current saturation characteristics, an Early Voltage of V_A≈10 V, h_fe-V_A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV_EBO≈9.6 V, and a cut-off frequency of f_t=17.8 GHz