无线ATM通信网的定时信息恢复技术研究

本文对无线ＡＴＭ通信网ＣＢＲ业务定时信息的恢复技术进行了研究，提出了异步剩余时间标签（ＡＲＴＳ）技术，并通过码速调整改善收端的ＣＢＲ业务时钟性能，给出了实现方案，同时提出采用ＡＲＴＳＦＩＦＯ吸收定时信息的延时抖动，由于无线ＡＴＭ通信网的误码率较大，其信元丢失率较高，本文在分析ＲＴＳ的多重码速调整特性基础上，还提出了利用收到相邻ＡＲＴＳ之间的差值规律来估计丢失的ＡＲＴＳ的新方法，理论计算和模拟结果表     

无线ATM系统的混合纠错方案及其在突发信道上的性能分析

本文提出了一种适用于无线ＡＴＭ系统的混合纠错方案：用ＲＳ码保护语音信号,用截短ＲＳ／混合Ⅱ型ＡＲＱ保护图像和数据。文中分析和仿真了这一混合纠错方案在突发信道上的性能。结果表明,利用ＲＳ码强的纠错能力,通过有限次的重传就可获得低的信元丢失率和传输时延。     

基于QOS的无线ATM协议结构及性能分析

有效，合理地分配信道资源和进差错控制是无线ＡＴＭ的两个关键技术，本文提出的基于ＱＯＳ的无线ＡＴＭ协议结构，在信元头加入３６比特的ＢＣＨ码用于差错控制，取代了标准ＡＴＭ信元头的ＶＣＩ／ＶＰＩ；在上行链路的信元头中增加１字节表示排队信息元次序，用于ＭＡＣ控制或信元排序。     

AAL5—CRC信元误插检测能力分析

分析了ＡＡＬ５ＣＰＣＳ－ＰＤＵ中ＣＲＣ的信元误插检测性能，结果表明，对于任何帧长不大于４Ｇｂｉｔ的数据帧，其检测不到信元误插的概率为２＾－３２。     

用FPGA实现ATM信元的字头处理

本文探讨了采用ＦＰＧＡ Ｘ３０００系列芯片实现独立于承载码流结构的ＡＴＭ信元字头处理器的可能性，针对ＦＰＧＡ处理速度相对低于可能的承载码流速率的问题，着重研究了字头ＨＥＣ字段生成，扰码，信元定界，解扰等过程的并行处理算法。     

基于ATM高速网介质访问控制方法的研究

本文分析了ＦＤＤＩ，Ｏｒｗｅｌｌ，ＡＴＭＲ，ＣＲＭＡ－Ⅱ，ＭｅｔａＲｉｎｇ等典型的高速网介质访问控制协议，提出了一个新的基于总线时间片的介质访问的控制方法－ＡＴＭＢ，并对ＡＴＭＢ的信元结构，局域网参考模型，控制方法作了进一步研究与分析，该方法基于没有对原网络节点的结构加以改变，它特别适合于高速网络的互连和与大网的转接。     

基于还宽需求预测的VBR业务速率分配

本文在对ＶＢＲ业务带宽需求预测的基础上，提出了一种综合考虑信元丢失率、信道利用率、缓冲延时和缓冲器空量需求等方面的ＶＢＲ业务频带动态分配的方法。对如何确定有关控制参数等问题，进行了研究，并就运用最佳线性预测和递归最小地乘法（ＲＩＳ）等估计理论，对ＶＢＲ业务流量速率的预测和控制，系统的性能作了分析和模拟。     

ATM适配层网络接口

给出了ＡＴＭ／ＡＡＬ网络接口功能图，采用单一的通用结构，此接口能处理几种不同的ＡＬＬ传输协议，从信元为单位支持ＣＢＲ和ＶＢＲ业务。     

无线ATM网络的逻辑链路控制技术

无线ＡＴＭ网络中，在信元进入ＡＴＭ网络层前，须通过逻辑链路控制（ＬＬＣ）层来消除无线信道的影响。本文对使用不同数据包长度和不同ＡＲＱ技术的ＬＬＣ方案进行了比较，并折中考虑了实现的复杂程度与所获得的性能，得出在不同的条件下应使用的数据包长度。本文还仿真了在瑞利衰落环境采用传统ＡＲＱ和码组合ＡＲＱ技术时系统的性能，结果表明码组合ＡＲＱ为一种简单而有效的方法。     

基于ATM宽带业务的ADSL接入研究

ＡＴＭ作为宽带网络的关键技术,取得了很大进展。ＡＤＳＬ则是目前很有潜力的网络接入了在ＡＤＳＬ上传输ＡＴＭ信元的原理和系统模型,在此基础上对各分层模块功能及相应协议进行了研究,并给出了在ＡＤＳＬ上传输ＡＴＭ时几种可能信道分配。     

前向纠错技术在高速PON中的应用研究

介绍了FEC（前向纠错）技术在PON（无源光网络）中的应用方式,分析了高速PON对FEC的要求,研究了适用于高速PON的FEC码型。通过分析常用RS和BCH等单码的误码率、码长和冗余度等性能,提出了适用于高速PON的FEC方案,并对实现原理和硬件复杂度进行了分析,用Verilog语言实现了该方案。仿真和分析结果表明,采用RS（255,223）码可以满足高速PON的应用需求,对其关键电路采用并行处理的方法完全可以实现10Gbit／s的速率。     

Improved FEC Code Based on Concatenated Code for Optical Transmission Systems

The improved three novel schemes of the super forward error correction(super-FEC) concatenated codes are proposed after the development trend of long-haul optical transmission systems and the defects of the existing FEC codes have been analyzed. The performance simulation of the Reed-Solomon(RS)+Bose-Chaudhuri-Hocguenghem(BCH) inner-outer serial concatenated code is implemented and the conceptions of encoding/decoding the parallel-concatenated code are presented. Furthermore, the simulation results for the RS(255,239)+RS(255,239) code and the RS(255,239)+RS(255,223) code show that the two consecutive concatenated codes are a superior coding scheme with such advantages as the better error correction, moderate redundancy and easy realization compared to the classic RS(255,239) code and other codes, and their signal to noise ratio gains are respectively 2～3dB more than that of the RS(255,239)code at the bit error rate of 1×10 -13 . Finally, the frame structure of the novel consecutive concatenated code is arranged to lay a firm foundation in designing its hardware.     

On the Performance of Short Forward Error-Correcting Codes

This letter investigates the performance of short forward error-correcting (FEC) codes. Reed-Solomon (RS) codes and concatenated zigzag codes are chosen as representatives of classical algebraic codes and modern simple iteratively decodable codes, respectively. Additionally, random binary linear codes are used as a baseline reference. Our main results (demonstrated by simulations and ensemble distance spectrum analysis) are as follows: 1) Short RS codes are as good as random binary linear codes; 2) Carefully designed short low-density parity-check (LDPC) codes are almost as good as random binary linear codes; 3) Low complexity belief propagation decoders incur considerable performance loss at short coding lengths. Thus, future work could focus on developing low-complexity (near) optimal decoders for RS codes and/or LDPC codes.     

OTN中FEC的优化设计及实现

光信号在OTN中传输时不可避免地会产生误码,而传统的反馈重传纠错方式因为需要反馈信道和重传等待时间,所以不适合在传输速率较高的OTN中使用。因此利用RS码及数据交织方法,设计了OTN中的FEC电路,同时为了提高电路性能,对电路中常用的有限域乘法器进行了优化。并通过仿真和FPGA验证电路功能的正确性。实验结果表明,所设计的FEC电路能够纠正传输中出现的误码,满足OTN技术要求。     

Joint iterative decoding of serially concatenated error controlcoded CDMA

Joint iterative decoding of multiple forward error control (FEC) encoded data streams is studied for linear multiple access channels, such as code-division multiple access (CDMA). It is shown that such systems can be viewed as serially concatenated coding systems, and that iterative soft-decision decoding can be performed successfully To improve power efficiency, powerful FEC codes are used. These FEC codes are themselves serially concatenated. The overall transmission system can be viewed as the concatenation of two error control codes with the linear multiple access channel, and soft-decision decoders are used at each stage. A variance transfer function approach applied to the analysis of this system captures the role of the component decoders in an overall iterative decoding system. We show that this approach forms a methodology to study the effects of the component codes as well as that of the iteration schedule. Analysis and simulation examples are presented for transmission systems that operate close to the Shannon limit and illustrate the accuracy of the analysis     

An efficient software implementation of a forward error correcting code

Today, Forward Error Correcting (FEC) codes are mainly implemented in hardware, and many believe that their complexity prohibits their software implementation. This paper presents in detail how the performances of a software implementantion can be significantly improved. Different levels of optimization which are independent of the working environment are presented and discussed. The coding throughput of 100 Mbps on an UltraSparc 1 shows that FEC codes can be easily added to multimedia applications without requiring dedicated hardware support. As a case study, we use FEC codes to protect AAL5-PDUs from cell losses in ATM networks.     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

宽带无线接入系统中长RS编解码的DSP设计与实现

介绍了宽带无线接入技术——本地无线城域网物理层的差错控制方案，基于伽罗华域乘法的并行计算，对IEEE802．16／a／d标准前向纠错中使用的RS码完成了DSP设计与实现，在TMS320C6416上予以实现，并使用不同的方法从不同角度测试其编译码的正确性。详细介绍了方案的原理和编程中解决的关键问题，给出了关键部分的源代码。最后根据开发板上的实测数据，给出了该方法在波特率为2．075Msym下达到的实时性能。这种方法不但可以用于本系统，还可以用于目前其他RS码实际应用的系统。     

一种LDPC码在光纤通信系统中的性能分析

针对超强前向纠错(FEC)技术在光纤通信系统中的应用,文章提出了一种构造简单、编码容易实现的低密度奇偶校验(LDPC)码的构造方法,并仿真验证了该LDPC码在光纤信道环境下的译码性能.与常用的RS(255,239)码相比,在相同的码效率下,所构造的码长为4 080的LDPC码能够获得比RS码高2 dB的编码增益.     

A Clean Slate Architecture Design for VANETs

In this paper, VANET applications have been classified according to their purpose. Furthermore, a clean-slate architecture specifically designed for VANETs has been introduced. The proposed non-layered context-aware ubiquitous architecture adapts dynamically to changes, is oriented to services (VANET applications) and has a flexible structure. The vehicle and environmental context-aware information as well as the VANET communication characteristics are designed for the proper operation of the applications. In addition, the performance of Automatic Repeat Request and Forward Error Correction (FEC) block codes with respect to the throughput efficiency has also been analyzed for a VANET following the proposed clean-slate architecture. The numerical results show that the proposed clean-slate architecture outperforms the traditional layered architecture with respect to the throughput efficiency for both error control schemes. FEC block codes are able to maintain high throughput efficiency over longer distances because the hop length extension technique is applied.