一类性能好的线性码的构造

利用有限域Fq上分圆多项式的分解特性，构造了一类q元线性码，这类线性码可以作为Reed-Solomon码和Chaoping Xing与San Ling所构造的线性码的推广。利用文中构造方法，可以得到更多性能优良的线性码。     

环Z4上线性循环码的深度谱

Etzion定义并研究了域Fq上线性码的深度谱，该文研究了环Z4上线性码与线性循环码的深度谱，证明了4^k12^k2型线性码的深度谱至少含有k1＋k2个非零值，并给出了一类4^k型线性循环码的深度谱为{n，n-1，…，n-k＋1}。     

基于二次乘法特征的射影线性码

基于有限域上的二次乘法特征构造了两类线性码，精确计算出了它们的参数和重量分布.结果表明，第一类线性码是射影三重码，且对偶码关于球填充界几乎最优；第二类线性码是射影二重码，且对偶码关于球填充界几乎最优.此外，本文还得到了一些自正交码和极小码，它们可分别用于构造量子码和安全高效访问结构上的密钥共享方案.     

环F2+uF2上线性码及其对偶码的二元象

利用环F2＋uF2上线性码C的生成矩阵给出了码C的对偶码C^┴及其Gray象Ф（C）的生成矩阵，证明了环F2＋uF2上线性码及其对偶码的Gray象仍是对偶码。并由此给出了一个环F2＋uF2如上线性码为自对偶码的充要条件。     

广义Hamming重量和等重码

本文将线性码的广义Ｈａｍｍｉｎｇ重量的概念推广到线性码上去，并导出了一种广义Ｅｌｉａｓ界，对于线性等重码，本文给出了其完整的重量谱系。     

准循环码和七个新的二元线性码

本文利用一类准循环码的结构进行计算机搜索，再加上通常的码的变换，共得到了七个新的二元线性码，它们都改进了文「１」中二元线性码极小距离的下界，其中有三个是最优的。     

有效书写记忆介质的编码构造方法

本文证明线性码的陪集构成的线性陪集码可以渐近达到有效书写记忆介质的容量，并且说明线性码的覆盖半径是有效书写记忆介质的线性陪集码的一个重要参数。本文同时给出有效书写记忆介质的纠错码的一种构造方法。     

一类三元线性分组码的译码

Ｐｌｅｓｓ［１］证明了三元（１２，６，６）Ｇｏｌａｙ码具有一种双层结构，并据此给出了该码的快速硬判决译码算法。本文推广了Ｇｏｌａｙ码的Ｐｌｅｓｓ结构，给出了由三元（ｎ，ｋ，ｄ）线性分组码构造的三元（３，ｎ＋ｋ，≥ｍｉｎ（ｎ，２ｄ，６））线性分组码，其中包括（１２，６，６）Ｇｏｌａｙ码和（１８，９，６）码，并以三元（１８，９，６）码为例给出了这类码的最大似然软判决译码算法。     

非主理想环F_p+vF_p上线性码的MacWilliams恒等式

研究了环F-p+vF_p上线性码的结构,证明了互为对偶的线性码的Gray象仍是互为对偶的线性码.定义了环F_p+vF_p上码的Lee重量、Hamming重量和广义对称重量分布计数器的概念,利用域F_p上线性码和对偶码重量分布的关系及Gray映射的性质,给出了该环上线性码及其对偶码之间的各种重量分布的Macwilliam...     

一种三元线性互补对偶码与自正交码的构造方法

有限域上线性互补对偶(LCD)码有良好的相关特性和正交特性,并能够防御信道攻击。自正交码是编码理论中一类非常重要的码,可以用于构造量子纠错码。该文研究了有限域F3上的LCD码。通过选取4种合适的定义集,利用有限域F3上线性码是LCD码或自正交码的判定条件,构造了4类3元LCD码和一些自正交码,并研究了这4类线性码的对偶码,得到了一些3元最优线性码。     

低时延RS-CC级联码的设计与实现

为提高手持无线电台的纠错和时延特性,考虑设计一种短码长RS-CC级联码.通过对Reed-Solomon码缩短和截断以及对卷积码删余,提出了一种低时延的级联码设计方案,并进行性能分析和软硬件实现.结果表明,在高斯信道下,当Eb/No达到4.2 dB时,能够实现10-4的误码率性能.设计的RS-CC级联码码长较短,编解码固有时延低,译码速度提升30％,适合低时延应用.     

Quasi-cyclic dyadic codes in the Walsh-Hadamard transform domain

A code is s-quasi-cyclic (s-QC) if there is an integer s such that cyclic shift of a codeword by s-positions is also a codeword. For s = 1, cyclic codes are obtained. A dyadic code is a code which is closed under all dyadic shifts. An s-QC dyadic (s-QCD) code is one which is both s-QC and dyadic. QCD codes with s = 1 give codes that are cyclic and dyadic (CD). We obtain a simple characterization of all QCD codes (hence of CD codes) over any field of odd characteristic using Walsh-Hadamard transform defined over that finite field. Also, it is shown that dual a code of an s-QCD code is also an s-QCD code and s-QCD codes for a given dimension are enumerated for all possible values of s.     

基于ARM核的嵌入式应用系统中的启动代码的编程

启动代码是针对基于32位ARM核的嵌入式系统的应用软件所编写的一段汇编程序,通过它将C语言编写的应用程序从FLASH存储器映射到SDRAM存储器,提高了系统的运行速度.启动代码实现了堆栈初始化、中断初始化、外围初始化等操作,大大提高了系统的开发效率及软件性能.本文详细介绍了对基于ARM核的32位嵌入式应用系统中启动代码的编程步骤,给出了一个具体的应用实例,并结合此例对代码的编译及调试过程进行了阐述.     

Concatenated parity and turbo codes

Turbo codes have an error floor that is caused by low-weight error events. Here, it is shown that a concatenated code with a simple rectangular parity-check outer code and a turbo inner code can significantly reduce the error floor. It is also shown that in several situations, the concatenated parity-check and turbo code performs significantly better than a turbo code alone     

Performance of Concatenated Dual-k Codes on a Rayleigh Fading Channel with a Bandwidth Constraint

The error rate performance, obtained on a Rayleigh fading channel, is determined and illustrated graphically for concatenated codes in which the outer code is a dual-kconvolutional code and the inner code is either a Hadamard block code or a block orthogonal code. Comparison of the performance of these two types of concatenated codes is made on the basis of the same bandwidth utilization. It is also illustrated that the concatenated dual-kcode yields a significant improvement in performance relative to the performance achieved with the inner code alone.     

CDMA随机多址接入技术研究

CDMA作为一种多址接入技术在无线网络中已广为应用,在多码CDMA和单码CDMA研究的基础上,构造了多码CDMA和单码CDMA在无线分组数据网络中的随机多址接入模型,并且分析了两种系统的吞吐率特性和归一化时延特性。结果证明单码CDMA和多码CDMA具有相同的多址接入性能。     

Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths

Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs. The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraint-based. An initial set of constraints on code generation are prescribed by the given processor model. Further constraints arise during code generation based on decisions concerning code selection, register allocation, and scheduling. Whenever possible, decisions are postponed until sufficient information about a good decision has been collected. The constraints are active in the "background" and guarantee local satisfiability at any point of time during code generation. This mechanism permits to simultaneously cope with special-purpose registers and instruction level parallelism. We describe the detailed integration of code generation phases. The implementation is based on the constraint logic programming (CLP) language ECLiPSe. For a standard DSP, we show that the quality of generated code comes close to hand-written assembly code. Since the input processor model can be edited by the user, also retargetability of the code generation technique is achieved within a certain processor class. This revised version was published online in July 2006 with corrections to the Cover Date.     

High-speed gray-binary and binary-Gray code convertors using electro-optic light modulators

A high-speed Gray-binary code convertor (g.b.c.) using electro-optic light modulators, which translates all bits of Gray code into binary code simultaneously, and a binary-Gray code convertor, which translates binary into Gray code, are described. A digital-analogue convertor using g.b.c. is also presented.     

Variable-length code construction for incoherent optical CDMA systems

The purpose of this study is to investigate the multirate transmission in fiber-optic code-division multiple-access (CDMA) networks. In this article, we propose a variable-length code construction for any existing optical orthogonal code to implement a multirate optical CDMA system (called as the multirate code system). For comparison, a multirate system where the lower-rate user sends each symbol twice is implemented and is called as the repeat code system. The repetition as an error-detection code in an ARQ scheme in the repeat code system is also investigated. Moreover, a parallel approach for the optical CDMA systems, which is proposed by Marić et al., is also compared with other systems proposed in this study. Theoretical analysis shows that the bit error probability of the proposed multirate code system is smaller than other systems, especially when the number of lower-rate users is large. Moreover, if there is at least one lower-rate user in the system, the multirate code system accommodates more users than other systems when the error probability of system is set below 10⁻⁹.     

一种半随机半代数的非正则LDPC码构造方法

LDPC码由于其卓越的纠错性能引起了学术界的广泛重视，当前LDPC所面临的一个主要问题是其编码复杂性的问题。本文给出了一种半代数半随机的非正则LDPC码构造方法，由该方法所构造的校验矩阵具有近似下三角特性，从而可以大大降低LDPC的编译码复杂性，同时具有与完全随机LDPC码相匹配的性能。