Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Hot-carrier effects in Hydrogen-passivated p-channel polycrystalline-Si MOSFET's

The dependence of hot-carrier effects on channel length and stress-bias voltage in hydrogen-passivated accumulation-mode p-channel polycrystalline-Si MOSFET's operating in the saturation region has been studied, Before stress, these devices exhibit a minimum value of current at VGS≈ 0 V but as VGSincreases above 0 V, they show an increase in (leakage) current due to field-enhanced generation of carriers near the drain. After stress, the current at VGS≈ 0 V increases slightly with respect to its pre-stress value. However, the current then monotonically decreases as VGSincreases above 0 V unlike the situation before stress. No change in reverse mode (source and drain reversed) characteristics and no change in the ON-state (VGS< 0 V) forward-mode characteristic was observed after stress. These observations are shown to be due to hot-carrier-induced acceptor-type interface states near the drain in forward-mode operation.     

Experimental results on submicron-size p-channel MOSFET's

We report results on p-channel MOSFET's with channel lengths as small as 0.5 µm. Using design criteria obtained from numerical simulation, the devices have been fabricated by a low temperature process with very short annealing times. Fabricated devices with submicron channel lengths are dominated by velocity saturation of holes. Comparing the drive capability of n- and p-channel devices, we find the intrinsic device currents to be within a factor of 1.4 for a channel length of 0.5 µm.     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Anomalous hot-carrier behavior for LDD p-channel transistors

It has previously been reported that gradual junction p-channel transistors can have shorter lifetimes under hot-carrier stress conditions than abrupt junction devices (see IEEE Trans. Electron Devices, vol. 39, p. 2290-98, 1992). Here, the work is extended to LDD (lightly doped drain) structures. p-MOS hot-carrier effects are examined for deep submicron structures with abrupt and LDD junctions. It is shown that, contrary to the case of n-MOS transistors, the lifetimes for hot-carrier stress of the LDD p-MOS transistors are actually shorter than their abrupt junction counterparts, in the range of LDD dopings examined here. This is explained in terms of two competing mechanisms, gate electronic injection, which decreases for the LDD junctions, and the size of the damage region in the oxide, which increases for the LDD junctions. It is concluded that using LDD-type structures for hot-carrier control does not automatically guarantee longer lifetimes     

Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography

Subhalf-micrometer p-channel MOSFET's with ultra-thin gate oxide (3.5 nm) have been fabricated using X-ray lithography and electron cyclotron resonance (ECR) plasma etching. The fabricated MOSFET's with 0.2-µm channel lengths show long-channel behavior and extremely high (200 mS/mm) transconductance.     

Measurements of residual defects and 1/f noise in ion-implanted p-channel MOSFET's

This paper describes the measurements of excess noise and residual defects of extremely low concentrations (<1 × 10⁹cm^-2) in ion-implanted p-channel MOSFET's. The activation energy and the density of the residual defects after high-temperature annealing were measured using a transient capacitance technique. The test FET's were ion-implanted with fluences of 5 × 10¹¹to 4 × 10¹²using³¹p⁺,¹¹B⁺, or²⁸Si⁺species. A post-implant anneal was carried out in an N2or an Ar ambient for 20 min at various temperatures. For¹¹B⁺-implanted MOSFET's after annealing above 1000°C, a high residual defect concentration was observed near the conduction band edge; whereas after annealing the defect density as a result of²⁸Si⁺or³¹p⁺implantation was equal to that of control MOSFET's. The density-of-state data agree with the equilibrium measurements of excess (1/f) noise power. The excess noise was measured as a function of the drain current. The distribution of1/fnoise power versus potential minimum of holes in the equilibrium condition is similar to that of interface state density. In nonequilibrium operation, a reduction of excess noise was achieved owing to the presence of buried channel created by ion implant.     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Single electron switching events in nanometer-scale Si MOSFET's

High-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 0.1 µm. These devices show discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps. The voltage and temperature dependence of this switching gives detailed information on the characteristics of the trap and its distance from the interface. This switching is a component of low-frequency noise in MOSFET's and may be an important limit to the performance of small transistors.     

Enhanced hot-carrier-degradation in LDD MOSFET's under pulsedstress

Hot-carrier degradation of lightly doped drain (LDD) MOSFET's under ac stress is investigated. Enhanced ac degradation occurs in LDD MOSFET's as well as in single-drain MOSFET's. However, there is a peculiar degradation mechanism in LDD MOSFET's. For single-drain MOSFET's, enhanced ac degradation appears in both threshold voltage and transconductance at stress drain voltages larger than a critical value. On the other hand, for LDD MOSFET's, although the enhanced degradation in threshold voltage and transconductance appears at stress drain voltages larger than a critical value, the enhanced degradation in transconductance appears even under stress drain voltages lower than the critical value. The difference in the ac-enhanced degradation between LDD and single-drain structures can be explained by a hot hole generated neutral-electron-trap model and the change in hot-hole-injected oxide region according to stress bias conditions     

MOSFET开态热载流子效应可靠性

综述了近年来ＭＯＳＦＥＴ的热载流子效应和可靠性的问题。总结了几种热载流子,并在此基础上详细讨论了热载流子注入（ＨＣＩ）引起的退化机制。对器件寿命预测模型进行了总结和讨论。为ＭＯＳＦＥＴ热载流子效应可靠性研究奠定了基础。     

Neutral electron trap generation under irradiation in reoxidizednitrided gate dielectrics

In this study we report for the first time results on neutral electron trap generation in reoxidised nitrided oxide dielectrics under various radiation doses and bias conditions and compare the results with the conventional oxides. We see very little electron trap creation in RNO dielectrics for radiation doses up to 5 Mrad (Si) and for bias fields up to ±2.5 MV/cm. We explain our results in RNO and oxide dielectrics using a three step defect creation model     

Submicron channel MOSFET's logic under punchthrough

The characteristics of n-channel MOSFETs that make use of the punchthrough current are considered in this paper. The current conduction mechanisms of the short channel MOSFET under the bias condition of punchthrough have been studied through the use of two-dimensional computer simulation. Experimental devices with channel lengths as short as 0.5 /spl mu/m were fabricated on a lightly doped substrate. Current-voltage curves of these devices showed pentode-like characteristics for smaller drain biases and triode-like characteristics for larger drain biases. A switching delay as small as 75 ps was obtained for a 13-stage ring oscillator composed of the submicron channel devices.     

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.     

High-performance p-channel poly-Si TFT's using electron cyclotronresonance hydrogen plasma passivation

This letter presents a summary of the first detailed investigation of electron cyclotron resonance (ECR) hydrogen plasma exposure treatments of p-channel poly-Si thin film transistors (TFT's). It is shown that ECR hydrogenation can be much more efficient than RF hydrogenation. Poly-Si p-channel TFT's fabricated at low temperatures (⩽625°C) and passivated with the ECR hydrogenation treatment are shown to exhibit ON/OFF current ratios of 7.6×10⁷, subthreshold swings of 0.62 V/decade, threshold voltages of -4.6 V, and hole mobilities over 18 cm²/V.s     

Effects of electric fields on annealing of radiation damage in MOSFET's

Radiation damage inp-channel MOS devices by 1.5 MeV electrons has been studied by thermal annealing in conjunction with electric fields between the metallic gate and the substrate. Both positive and negative gate biases retard the process of annealing. Annealing with negative gate bias reveals 1) that during thermal annealing the majority of the electrons that recombine with the positive charge in the oxide originate from the conduction band of the silicon, and 2) that during irradiation a great number of ionized electrons that remain in the oxide do not recombine with the holes, but are trapped in weakly bound states. The effect of positive bias on annealing of radiation damage is obscured by the positive charge induced due to positive bias-temperature treatment alone. No effect of drain-to-source potential on annealing has been observed.