基于ARM+Linux平台的USB指纹采集模块设计实现

采用FPS200指纹采集芯片的USB模式,内部ROM功能在ARM+Linux平台下实现指纹的采集,完成了硬件和软件的设计,而对于软件需要完成USB的驱动程序和应用程序的设计.FPS200的USB功能利用芯片的手指自动检测电路探测是否有指纹来产生中断,将ISR(中断状态寄存器)的值传到端点2.为了快速地响应中断,利用异步...     

Towards intrinsically universal asynchronous CA

We consider asynchronous one-dimensional cellular automata (CA). It is shown that there is one with von Neumann neighborhood of radius 1 which can simulate each asynchronous one-dimensional cellular automaton. Analogous constructions are described for α-asynchronous CA (where each cell independently enters a new state with probability α, and for “neighborhood independent” asynchronous CA (where never two cells are updated simultaneously if one is in the neighborhood of the other). This also gives rise to a construction for so-called fully asynchronous CA (where in each step exactly one cell is updated).     

Construction universality in purely asynchronous cellular automata

Universality in cellular automata (CAs), first studied by von Neumann, has attracted much research efforts over the years, especially for CA employing synchronous timing. This paper proposes a computation- and construction-universal CA with a von Neumann neighborhood that is updated in a purely asynchronous way, rather than by the conventional but less efficient way of simulating synchronous CAs on asynchronous CAs. The proposed asynchronous CA is capable of implementing self-reproducing machines. Our model employs strongly symmetric cells with 15 states.     

基于Petri网的异步电路设计关键技术研究

Petri网是异步并发现象建模的重要工具,以异步处理器为代表的异步电路以其在解决时钟扭曲,低功耗方面的优势受到越来越广泛的关注,异步电路设计的主要问题之一是缺乏成熟的EDA工具支持异步电路的设计风格,采用基于信号转换图(STG)的方法,完成了一个基于握手协议的异步控制部件的Petri网模型建立以及仿真和实现。并进一步给出了一个异步FIFO的设计应用实例。通过标准的时序仿真方法,得到的仿真结果表明上述方法能够很好地完成异步电路的设计而且在综合效率和资源利用上有明显的改进。     

基于去同步技术的异步8051设计与实现

随着半导体工艺的发展,同步电路面临的时钟偏差、功耗等问题日益突出,异步设计方法得到广泛研究和关注。去同步技术可以方便地实现从同步向异步的转化,成为很有前途的异步电路设计方法。基于去同步技术设计实现了一款异步8051微控制器,着重介绍了基于去同步技术的设计流程与异步控制器设计方法。分析表明,在相同的电压、温度条件下,该异步8051性能与同步8051相当,而功耗约为1/2。     

异步FIFO控制器的设计

异步FIFO是一种先进先出电路,可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点,以降低电路中亚稳态出现的概率为主要目的,提出了一种格雷码计数器的技术,通过仿真验证,有效地实现了异步FIFO控制器的设计。该设计将大大提高工作频率和资源利用率。     

通用异步串行通信电路的VHDL设计与实现

本文分析了异步串行通信的帧格式。利用VHDL设计出异步串行通信电路，并通过计算机仿真和实验证明了设计的正确性。     

一种机动目标跟踪的异步航迹融合算法

为实现机动目标跟踪,提出一种异步序贯航迹融合算法。融合中心包含匀速和匀加速2种融合模型,均通过信息去相关方法实现序贯航迹融合,并利用调整过程噪声的方法抑制融合发散。对匀加速融合模型的加速度估计进行显著性检验,实现机动检测。当检测到机动时输出匀加速融合模型的结果,反之输出匀速融合模型的结果。仿真结果表明,该算法能实现对机动目标的稳定跟踪,具有较高的跟踪精度。     

一种基于ASIC的高速异步FIFO设计

分析了异步FIFO的结构和关键技术,在与利用格雷码作为异步FIFO指针编码对比的基础上,提出了一种采用移位码编码方式的FIFO,不仅减小了亚稳态出现的概率,也简化了电路结构,降低了电路面积和功耗,在此基础上也缩短了电路的关键路径,工作频率明显提升。根据仿真和综合结果显示,本文设计的FIFO工作性能稳定可靠。     

An Implementation of Constructive Synchronous Programs in POLIS

Design tools for embedded reactive systems commonly use a model of computation that employs both synchronous and asynchronous communication styles. We form a junction between these two with an implementation of synchronous languages and circuits (Esterel) on asynchronous networks (POLIS). We implement fact propagation, the key concept of synchronous constructive semantics, on an asynchronous non-deterministic network: POLIS nodes (CFSMs) save state locally to deduce facts, and the network globally propagates facts between them. The result is a correct implementation of the synchronous input/output behavior of the program. Our model is compositional, and thus permits implementations at various levels of granularity from one CFSM per circuit gate to one CFSM per circuit. This allows one to explore various tradeoffs between synchronous and asynchronous implementations.     

异步电路的计算机辅助设计软件

异步电路由于没有时钟频率的限制,所以较同步电路有很多优点,其研究也越来越广泛,是未来解决计算机CPU设计的一种重要方案。异步电路的计算机辅助设计软件代表了异步电路当前研究的前沿,通过研究这些软件可以对异步电路的模型有更为深入的认识。论文整理列举了有关异步电路的63种软件工具,并将其分为设计、仿真、相关设计工具、前端设计、综合和验证6个方面。最后,在这些软件中选取两种设计软件对一个简单的例子进行了设计实现,以体现异步电路的设计特点。     

Grids and universal computations on one-dimensional cellular automata

This article shows how universal computations can be achieved on one-dimensional cellular automata. We are interested in intrinsic universality: we want a CA in which any other CA can be represented and simulated with no intermediate coding relevant to another computation model. We first abstract the space-time diagram in favor of the dependency graph. Then we show how such a dependency graph (via treillis automata) can be realized by what is called a grid, leading to a simple uniform simulation. Finally, we exhibit a very simple universal brick that can be used in grids to obtain an intrinsic universal CA.     

基于Lyapunov理论的异步电机定子绕组匝间短路故障检测系统设计

为实现对定子绕组匝间短路故障行为的精准识别，确保异步电机的稳定运行状态，设计了基于Lyapunov理论的异步电机定子绕组匝间短路故障检测系统。在DSP外围电量回路中，设置ARM处理器与步进电机驱动模块，采用模数转换单元结构，调节电量互感装置的实时运行状态，实现对异步电机定子绕组匝间短路故障检测系统硬件设计。根据Lyapunov函数定义条件，确定Nussbaum增益参数取值范围，在此基础上，定义Lyapunov算法模型，再通过计算故障预测特征的方法，求解定子绕组的短路故障电压方程与匝间电感参数，对定子绕组匝间短路故障特征进行分析，实现异步电机定子绕组匝间短路故障检测。实验结果表明，所设计系统可以有效控制定子绕组匝间短路故障电流和电压检测结果与标准检测结果之间的差值水平，能够精准识别定子绕组匝间短路故障行为，保障异步电机的稳定运行状态。     

FPGA异步FIFO设计中的问题与解决办法

通过分析异步FIFO的基本结构和工作原理,以降低亚稳态的出现频率、充分利用异步FIFO的内存资源为主要目的,提出一种在FPGA内部实现的异步FIFO设计方法。本文在传统设计的基础上提出一种新颖的电路结构来准确判断空／满标志位的产生,即检测加计数器的方法;并用QuartusⅡ对其进行仿真,得到了比较好的性能。     

抗差分功耗分析攻击的AES S盒电路设计

提出一种抗差分功耗分析攻击的高级加密标准(AES)异步S盒电路。采用复合域算法实现精简的S盒结构,通过引入单轨异步流水线降低整个S盒的功耗,在单轨电路中局部采用异步双轨电路,利用随机数控制下的数据扰乱机制,改善电路的抗差分功耗分析攻击性能,建立S盒差分功耗分析攻击仿真平台,对设计的相关性能进行了仿真验证和测试。     

基于单片机的星三角电动机启动电路设计

设计一种基于单片机控制的电动机星三角启动电路.本电路采用单片机作为控制器,控制三相异步电动机的星三角启动.该控制电路可通过按键启动和关闭电动机,同时还可设置电动机星三角转换的延迟时间.当通过按钮启动电动机后,单片机将自动实现三相异步电动机启动电路的星三角转换.该控制电路还以级联共阴数码管为显示器,实现电动机状态与星三角转换延迟剩余时间的显示,具有优良的人机界面.     

异步子字并行乘累加单元的设计与实现

异步电路能很好地解决同步集成电路设计中出现的时钟扭曲和时钟功耗过大等问题。本文采用异步集成电路设计方法设计了一款32位异步子字并行乘累加单元,并在0.18μm工艺条件下实现了该单元。通过使用特殊的部分积译码电路,该乘累加单元能支持多种子字并行模式,适用于多媒体处理。评测结果表明,异步乘累加单元的性能和功耗指标均优于采用同样结构的同步乘累加单元。     

Asynchronous cellular automata and dynamical properties

In this article the dynamical behaviour of asynchronous cellular automata (CA) is formally studied. Classical CA properties as surjectivity, injectivity, sensitivity, expansivity, transitivity, dense periodic orbits and equicontinuity have been adapted to the asynchronous case. We also deal with stability of properties with respect to perturbations on some update sequences which produce a significant dynamical behaviour.     

A simple proof technique for priority-scheduled systems

A simple proof method is presented for proving invariance properties of concurrent programs in priority-scheduled systems. This method is illustrated by using it to establish the correctness of a simple wait-free consensus algorithm for priority-scheduled uniprocessor systems. This consensus algorithm is of interest in its own right because is shows that atomic read and write operations are universal in priority-scheduled uniprocessor systems, i.e., they can be used to implement any shared object in such a system in a wait-free manner. This stands in contrast to fully asynchronous systems, where strong synchronization primitives such as compare-and-swap are needed for universality.     

Three generations of asynchronous microprocessors

We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The asynchronous circuits we use are called quasidelay-insensitive (QDI) circuits. A QDI circuit involves no assumption about, or knowledge of, delays in operators and wires, except for isochronic forks, which the designer assumes have similar delays on the different branches. QDI circuits are the most conservative asynchronous circuits in terms of delays.