Compact sub-hertz OTA-C filter design with interface-trap charge pump

Single-ended and differential operational transconductance amplifier (OTA) configurations are biased with MOSFET interface-trap charge-pumping (ITCP) current generators to achieve very low transconductances for tunable sub-hertz operational transconductance amplifier-capacitor (OTA-C) filter implementation. This paper reviews the basics of ITCP current generation and presents the transconductors and the OTA-C filter configurations based on these transconductors. One of the filters is a low-pass with an experimentally determined lowest cutoff frequency of 0.18 Hz, and the other is a fully differential bandpass with individually tunable lower and upper cutoff frequencies measured down to 0.3 Hz. The former has one 15-pF filter capacitor, and measures 0.0346 mm/sup 2/, whereas the latter contains four such capacitors and occupies 0.188 mm/sup 2/ silicon. Experimental evaluation also includes offset, harmonic distortion, and noise performance.     

An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.     

GaAs CCD's with transparent (ITO) gates for imaging and optical signal processing

Sputtered indium tin oxide (ITO) film is used as the transparent Schottky gate material for GaAs CCD's. In addition the gigahertz clocking-rate capability of GaAs CCD's makes them attractive for high-speed optical signal processing applications. The operation of the GaAs CCD's with fixed-aperture mask over the transparent gates is reported here. Such structures are basic components of a GaAs CCD-based electrooptic processor (EOP).     

Evaluation of current density distribution in MESFET gates

An analytical evaluation of the distribution of the current density both along the gate finger and perpendicular to the metal/semiconductor interface in MESFET transistors is reported for the case of forward-biased gate junctions. Examples are given for two gate resistances per unit length to evidence the current crowding effect which appears near the gate pad on increasing the gate resistance.     

注氮剂量对SOI材料埋氧中电荷密度的影响

为对SIMOX SOI材料进行抗总剂量辐照加固,可向材料的埋氧（BOX）层中注入一定剂量的氮元素。但是,研究发现,注氮埋层中的初始电荷密度皆为正值且密度较高,而且随着注氮剂量的增加而上升。注氮埋层中较高的正电荷密度可归因于氮在退火过程中在Si-BOX界面的积累。另外,与注氮埋层不同的是,注氟的埋层却显示出具有负的电荷密度。为得到埋层的电荷密度,测试用样品制成金属-埋氧-半导体(MBS)电容结构,用于进行高频C-V测量分析。     

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density.The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.     

Gate oxide reliabilities in MOS (metal-oxide-semiconductor) structures with Ti-polycide gates

We have investigated the thermal degradation of gate oxide in metal-oxide-semiconductor (MOS) structures with Ti-polycide gates. We found that the Ti-diffusion into the underlying polysilicon and consequently to the gate oxide occurs upon thermal cycling processes, which results in the dielectric breakdown of the gate oxide. We also found that the Ti-diffusion is suppressed by the employment of the thin (about 5 nm) titanium nitride (TiN) diffusion barrier layer, which consequently improved the reliability characterisitics of gate oxide significantly.     

Improved prediction of interface-trap generation in NMOST's

Hot-carrier-induced interface-trap generation in NMOSFET's is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is applicable in existing circuit simulators. From the (time dependent) voltages and currents, available in a circuit simulator, we predict the number of generated interface traps. Our prediction method has been checked in more than a hundred experiments on NMOSFET's with 0.2-2.0-μm length, 0.8-10-μm width, and 5.5-25-nm oxide thickness     

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas (2DEG) density and surface potential for AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMT). The developed model includes important parameters like polarization charge density at oxide/AlGaN and AlGaN/GaN interfaces, interfacial defect oxide charges and donor charges at the surface of the AlGaN barrier. The effects of two different gate oxides (Al₂O₃ and HfO₂) are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al₂O₃ dielectric have an advantage of significant increase in 2DEG up to 1.2×10¹³ cm^-2 with an increase in oxide thickness up to 10 nm as compared to HfO₂ dielectric MOSHEMT. The surface potential for HfO₂ based device decreases from 2 to -1.6 eV within 10 nm of oxide thickness whereas for the Al₂O₃ based device a sharp transition of surface potential occurs from 2.8 to -8.3 eV. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model, the device is simulated in Silvaco Technology Computer Aided Design (TCAD) showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for GaN MOSHEMT devices for performance analysis.     

Assessment of oxide charge density and centroid from Fowler-Nordheim derivative characteristics in MOS structures after uniform gate stress

A new method for the extraction of the oxide charge density and distribution centroid based on the exploitation of the Fowler plot derivative characteristics is proposed. The comparison with the DiMaria method confirms the overall consistency of the new approach. The presence of negative charge within the oxide is shown to be responsible for an increase in the apparent Fowler barrier height after uniform gate stress.     

Determination of trapped oxide charge in flash-type EEPROMs with heavily oxynitrided tunnel oxide films

Flash-type EEPROMs with rapid thermal oxide (RTO) and rapid thermal oxynitrided oxide (RTONO) films are fabricated. The oxide trap density in the program and erase (P/E) cycles is determined by the shifts in I-V curves for the source-gate and drain-gate edges, respectively. The RTONO flash cell shows a drastically reduced trap density of less than 3*10/sup 12//cm/sup 2/ after 10/sup 4/ P/E cycles. This value is one order smaller than that of the RTO flash cell. This smaller oxide trap density originates in the stable Si-N bond formation near the SiO/sub 2/-Si interface, and results in lower threshold voltage shifts.<>     

Study of interface state density and effective oxide charge inpost-metallization annealed SiO2-SiC structures

A systematic study of post-metallization annealing (PMA) effect on the quality of thermal SiO₂ on p-type 6H- and 4H-SiC has been carried out. A simultaneous quasi-static hi-lo frequency capacitance-voltage method has been employed to measure the total effective oxide charge (N_eff) and interface state density (D _it). To ensure accurate results, D_it was measured at 350°C which, depending on the hole capture cross sections, should enable the measurement of interface states located in the band gap as deep as 1.3-1.5 eV from the valence band edge. The dependence of N_eff and D_it on annealing temperature and ambient as well as the effect of thermal and sputtered gate metal on the oxide quality are reported. It is shown that N_eff values close to the detection limit due to the uncertainty in SiC electron affinities and D_it values below 1×10¹¹ cm^-2/eV deep in the band gap can be reproducibly obtained for both p-type 6H- and 4H-SiC     

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.     

Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation

A new experimental method is proposed to distinguish the electron-trapping effect in the gate oxide from the interface-trap generation effect in hot-electron-induced nMOSFET degradation. In this method, by selecting the appropriate bias conditions, hot electrons and/ or hot holes are intentionally injected into the oxide region above the channel outside the drain layer, which affects MOSFET characteristics such as threshold voltage and transconductance. The negative charges of electrons trapped in the oxide during hot-electron injection are completely compensated for by the positive charges of subsequently injected and trapped holes, and the trapped electron effect in the degradation is eliminated. Using this method, the causes for hot-electron-induced transconductance degradation (Δgm/gm) are analyzed. As the degradation increases, the trapped-electron effect decreases, and the generated interface-trap effect increases. The relationship of (Δgm/gm)_{it}, =A(Δgm/gm) --Bis obtained, where (Δgm/gm)_{it} is gmdegradation due to generated interface-traps, andAandBare fixed numbers. Furthermore φ_{it}/λ (the ratio of the critical value in hot-electron energy for interface-trap generation to the mean free path of hot electrons in Si) is experimentally obtained to be 5.7 × 10⁶eV/cm. Using λ = 9.2 nm [1], a value of φ_{it} = 5.2 eV is derived.     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

Lateral profiling of interface traps and oxide charge in MOSFETdevices: charge pumping versus DCIV

An improved oxide-charge and interface-trap lateral profiling charge pumping technique (iLPCP) is described. Erase-induced oxide charge and interface traps are investigated in flash EPROM devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results. A comparative study of iLPCP and of an existing direct current (DCIV) technique for lateral profiling of interface traps is conducted: both erase- and program-induced interface traps are investigated in flash EPROM devices. The results indicate that 1) iLPCP probes a much bigger portion of the gate region; 2) iLPCP probes a wider energy range; 3) DCIV is more sensitive deep in the channel and thus complements iLPCP     

Data retention characteristics of MANOS-type flash memory device with different metal gates at various levels of charge injection

We investigated the impact of charge injection and metal gates (Al and Pt) on the data retention characteristics of metal–alumina–nitride–oxide–silicon (MANOS) devices for NAND flash memory application. Through the theoretical and experimental results, the highly injected charge (ΔV_TH) could cause the band bending of Al₂O₃, which reduced the tunneling distance across Al₂O₃. Thus, the dominant charge loss path is not only toward SiO₂ but also toward Al₂O₃ direction. Compared to low-metal work function (Ф_M), ONA stack with high-Ф_M showed better data retention characteristics, even if ΔV_TH is high. This could be explained by Fermi level alignment for different Ф_M, which results in the reduction of electric field across the Al₂O₃ compensated by the ΔФ_M (Ф_Pt ? Ф_Al).     

Surface current and charge density induced on aircraft

The usefulness of the geometrical theory of diffraction (GTD) in computing the surface current and charge density induced on aircraft is illustrated. This is a high-frequency solution for an arbitrary incident plane wave and fuselage observation points. A pattern is presented for an arbitrary incident plane wave as well as a series of frequency and time domain plots for roll plane incidence. A 3-dimensional pattern is presented for plane wave incidence (as a function of incidence angle) as well as examples of roll plane results in both the frequency and time domain.     

Injection of charge into the archetype organic hole transporting material TPD at the electrical contacts with ITO and Al

A study of the current–electric field characteristics of single layer structures Quartz/ITO/TPD/Al and Quartz/Al₁/TPD/Al₂, containing the vacuum evaporated films of a diamine derivative (TPD) used commonly as a hole-transporting material in organic light emitting diodes, was carried out. The currents are dominated by injection of holes independent on the bias of the electrical contacts. In addition to an obvious asymmetry in the currents for ITO⁺ and ITO⁻ biased contacts, a distinct asymmetry for aluminum ${\text{Al}}_1^{+}$ and ${\text{Al}}_1^{-}$ biased contact is observed. The results have been interpreted in terms of the injection-limited current theory accounted for the electrode and bi-molecular recombination.     

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism(NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are:(1) with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.(2) Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style(i.e.spacing between transistors and n-well contact area).(3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.