Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the ‘clock cycling scenario’, which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The ‘data cycling scenario’ with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the ‘data cycling scenario’ are shown to have less body charge loss through the switching cycles than under the ‘clock cycling scenario’.     

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits

This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.     

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.     

Noise analysis methodology for partially depleted SOI circuits

In partially depleted silicon-on-insulator (PD-SOI) technology, signal switching history and intial state of the circuit nodes can affect the device body voltage and also cause parasitic BJT leakage currents, which can lead to significant increase in noise propagation and noise failures. In this brief we explore the effects of input switching history, initial circuit conditions and the parasitic BJT device on all steps in a traditional noise analysis methodology: noise injection, noise propagation, and noise failure criterion. We present a new noise analysis methodology to account for the floating body and the BJT effects in PD SOI technology. We demonstrate the new technique on an industrial microprocessor design in PD SOI and show that the current noise analysis methods do not account for 56% of noise fails.     

Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits

The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 μm technology device a good matching with the fsm was found.     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

On the temperature dependence of hysteresis effect in floating-bodypartially depleted SOI CMOS circuits

This paper presents a detailed study on the temperature dependence of the hysteresis effect in static CMOS circuits and pass-transistor-based circuits with floating-body partially depleted (PD) silicon-on-insulator (SOI) CMOS devices. Basic physical mechanisms underlying the temperature dependence of hysteretic delay variations are examined. It is shown that, depending on the initial state of the circuit, the initial circuit delays have distinct temperature dependence. For steady-state circuit delays, the temperature dependence is dictated solely by the various charge injection/removing mechanisms into/from the body. The use of the cross-coupled dual-rail configuration in pass-transistor-based circuits is shown to be effective in compensating and reducing the disparity in the temperature dependence of the delays     

Influence of uniaxial tensile strain on the performance of partially depleted SOI CMOS ring oscillators

The influence of uniaxial tensile strain on the performance of advanced partially depleted silicon-on-insulator CMOS ring oscillators is reported. Strain is applied either perpendicular or parallel to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. Interestingly, the standby power dissipation of the ring oscillators increases for both parallel and perpendicular strains due to changes in the gate tunneling currents with strain. The on-state power dissipation decreases with parallel strain and increases with perpendicular strain consistent with the expected changes in the inversion layer piezoresistance. The speed of the ring oscillators improves with perpendicular strain and degrades with parallel strain, which can also be understood in terms of the piezoresistance changes.     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

Fully depleted SOI CMOS logic gates for low-voltage applications

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.     

On the transient operation of partially depleted SOI NMOSFET's

The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices     

EOS/ESD reliability of partially depleted SOI technology

A model for predicting the electrostatic discharge (ESD) protection level of PD-SOI MOSFETs and diodes is presented along with data to support the model. The form of the model is compatible with circuit simulators. An important design rule for layout of multifinger SOI ESD protection MOSFETs has been derived from the model. We present experimental data to support this design rule     

Hysteresis effect in pass-transistor-based, partially depleted SOICMOS circuits

This paper presents a detailed study on the hysteretic delay variations of pass-transistor-based circuits with floating-body partially depleted silicon-on-insulator CMOS devices. It is shown that the pass-transistor can be conditioned into a initial state with extremely high body voltage (exceeding the power supply voltage V_DD ), thus resulting in highly hysteretic delay variations when the body subsequently loses charges through the switching cycles. Basic physical mechanisms underlying the hysteretic circuit behavior and its frequency dependence are examined. Different initial states of the circuit are shown to cause large delay disparity at the beginning of the switching activity, yet they converge as the circuit approaches steady state. Use of a cross coupled dual-rail circuit configuration is shown to be very effective in reducing the hysteretic delay variation and its frequency dependence     

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Low-voltage arithmetic units based on fully depleted SOI CMOS nanotransistors

Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor.     

Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs

Low frequency excess noise associated to gate-induced floating body effect is for the first time reported in Partially Depleted SOI MOSFETs with ultrathin gate oxide. This was investigated with respect to floating body devices biased in linear regime. Due to a body charging from the gate, a Lorentzian-like noise component superimposes to the conventional 1/f noise spectrum. This excess noise exhibits the same behavior as the Kink-related excess noise previously observed in Partially Depleted devices in saturation regime.