Development of an etchant for selectively etching TiWNxin the presence of electroplated 95%Pb-5%Sn solder

Shrinking die sizes and increasing I/O density is motivating the push toward flip chip packages. A flip chip interconnection system with a under bump metallurgy stack containing sputtered TiWN_X/sputtered Cu/electroplated Cu stud/electroplated 95%Pb-5%Sn was developed. An important step in the above process is the selective etching of the sputtered Cu bus layer and the TiWN_X barrier layer, in the presence of the Pb-Sn solder. The Cu bus layer was selectively etched using commercial etchants. However, no commercial etchants were available for selectively etching the TiWN_X layer, H₂O₂-NH₄OH based etching systems, popularly known as Standard Clean-1 cleaning solutions, have been extensively used to clean silicon wafers in front end wafer fabrication where only trace metal contamination exists. Since metals like lead, copper, titanium, tin and tungsten catalyze the heterogeneous decomposition of the peroxide, the unstable H₂O₂-NH₄OH based etching systems are rarely used to etch metal films. In this paper the development of a H ₂O₂-NH₄OH based etchant to selectively etch the sputtered TiWN_X films in the presence of electroplated 95%Pb-5%Sn solder bumps is discussed. A 2³ full factorial experiment with mid point was conducted to establish the etchant composition, as well as process temperature, that give satisfactory responses with respect to etch time, permissable undercut of the Cu stud (caused by the NH₄OH), and acceptable bump shape after reflow. Statistical analysis was used to understand the significant factors influencing the etch rate and undercut. An etchant containing 6% by volume of 30%-H₂O₂ and 0.75% by volume of 30%-NH₄OH operated at a temperature of 37°C was found to give satisfactory results     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Void control during plating process and thermal annealing of through-mask electroplated copper interconnects

The quality of the sputtered copper film, which serves as the seed layer for sequent electroplating, becomes critical when the size of crack on the surface of the sputtered film is close to the feature size of the electroplated copper interconnect. The crack results in void formation in electroplated copper before thermal annealing and this phenomenon limits attainable highest anneal temperature. To solve this problem, the sputtered seed layer was slightly etched before electroplating process and a TaN passivation layer was deposited on the electroplated Cu interconnect before thermal annealing. Those processes not only suppressed void formation during the electroplating and annealing process at 300 °C, but also resulted in lower electrical resistance in the copper interconnects.     

Kirkendall voids formation in the reaction between Ni-doped SnAg lead-free solders and different Cu substrates

The reactions between Sn2.5Ag solder doped with different levels of Ni (0-0.1 wt.%) and two different types of Cu substrates, electroplated Cu and high-purity Cu substrates, were studied. The main objective was to investigate the effect of Cu substrate and the effect of Ni additions on the formation of Kirkendall voids within the Cu₃Sn phase. Reaction conditions included one reflow and subsequent aging at 160 °C for up to 2000 h. After reflow, Cu₆Sn₅ was the only reaction product observed for all the different solders and substrates used. During aging, both Cu₆Sn₅ and Cu₃Sn formed. Nevertheless, Kirkendall voids were observed only when the electroplated Cu was used, and was not observed when high-purity Cu was used. It was proposed that impurities in electroplated Cu helped the nucleation of these voids. The Ni additions made the Cu₃Sn layer thinner. For the case of the electroplated Cu substrates, the amount of Kirkendall voids decreased correspondingly with the Ni additions.     

Interaction Between Ni and Cu Across 95Pb-5Sn High-Lead Layer

Ni/95Pb-5Sn/Cu ternary diffusion couples were used to investigate the cross-interaction between Ni and Cu across a layer of 95Pb-5Sn solder. High-lead solder layers with a thickness of 100 μm or 400 μm were electroplated over Cu foils. A pure Ni layer (20 μm) was then deposited over the as-deposited high-lead solder surface. The diffusion couples were then aged at 150°C to 250°C for different periods of time. With this technique, the diffusion couples were assembled without experiencing any high-temperature process such as reflow, which would have accelerated the interaction and caused difficulties in analysis. This study revealed that massive spalling also occurred during aging even though reflow was not used. The massive spalling began with the formation of microvoids. When the microvoids had congregated into large enough voids, intermetallic compounds (Cu₃Sn) started to spall from the interface. This spalling phenomenon occurred sooner with increasing temperature and decreasing solder volume.     

Crystallographic study on self-annealing of electroplated copper at room temperature

Self-annealing in electroplated Cu films is the dramatic evolution of the microstructure in electroplated Cu near room temperature, and it occurs during a transient period of hours following the electroplating process. This study discusses the change of grain size and orientation in self-annealing of Cu films electroplated by an additive-free sulfate bath using X-ray diffraction and electron backscatter diffraction techniques. We found that the self-annealing started at the interface between the substrate and the electroplated Cu film. Immediately after the electroplating process, orientation of the Cu grains in the region near the interface was similar to that of the substrate. This indicates that the grain growth was affected by the substrate. Then, grain growth and change in orientation of the electroplated Cu film at room temperature became independent from the orientation of the substrate. The electroplated Cu film had many high-angle-grain boundaries (HAGBs) before incubation, and the fraction of HAGBs reduced as incubation time increased. Self-annealed Cu grains in the electroplated Cu film had many multiple twins, which came from low stacking-fault energy of Cu.     

Crystallization and failure behavior of Ta-Ni nanostructured/amorphous diffusion barriers for copper metallization

This work examines the thin-film properties and diffusion barrier behavior of sputtered Ta-Ni films, aiming at depositing highly crystallization-resistant and conductive diffusion barriers for Cu metallization. Structural analysis indicates that the as-deposited Ta-Ni films indeed have a glassy structure and are free from highly resistive intermetallic compounds. Examining Si/Ta-Ni/Cu stacked samples reveals that thermally induced failure of amorphous Ta-Ni barriers is triggered by the barrier’s reaction with the silicon substrate at temperatures around 700°C. The effectiveness of the amorphous Ta-Ni thin film thus can be substantially enhanced by effectively blocking diffusion of copper toward the underlying silicon.     

Impact Testing of Sn-3.0Ag-0.5Cu Solder with Ti/Ni(V)/Cu Under Bump Metallization After Aging at 150°C

Nonmagnetic Ni(V) metal and low consumption rate with solders are the advantages of sputtered Ti/Ni(V)/Cu under bump metallization (UBM). However, a Sn-rich phase (“Sn-patch” herein) can form in the Ni(V) layer after reflow and aging. In lead-free solder, Sn-patches form and grow more quickly than in Sn-Pb solder. Thus, the effect of Sn-patches on solder joint reliability becomes critical. In this study, Sn-3.0Ag-0.5Cu solder was reflowed with Ti/Ni(V)/Cu UBM at 250°C for 60 s, and then aged at 150°C for various durations. A high-speed impact test was introduced to evaluate solder joint reliability. After impact testing, it was found that, the larger the Sn-patch, the greater the propensity of the solder joint to suffer brittle fracture. The correlation between Sn-patch and solder joint reliability is discussed.     

Electroless CoWP as a Diffusion Barrier between Electroless Copper and Silicon

In this work, an electroless CoWP film deposited on a silicon substrate as a diffusion barrier for electroless Cu and silicon has been studied. Four different Cu 120 nm/CoWP/Si stacked samples with 30, 60, 75, and 100 nm electroless CoWP films were prepared and annealed in a rapid thermal annealing (RTA) furnace at 300°C to 800°C for 5 min. The failure behavior of the electroless CoWP film in the Cu/CoWP/Si sample and the effect of CoWP film thickness on the diffusion barrier properties have been investigated by transmission electron microscopy (TEM), scanning electron microscopy (SEM), X-ray diffraction (XRD), and sheet resistance measurements. The composition of the electroless CoWP films was 89.4 at.% Co, 2.4 at.% W, and 8.2 at.% P, as determined by energy dispersive X-ray spectrometer (EDS). A 30 nm electroless CoWP film can prevent copper penetration up to 500°C, and a 75 nm electroless CoWP film can survive at least up to 600°C. Therefore, increasing the thickness of electroless CoWP films effectively increases the failure temperature of the Cu/CoWP/Si samples. The observations of SEM and TEM show that interdiffusion of the copper and cobalt causes the failure of the electroless CoWP diffusion barriers in Cu/CoWP/Si during thermal annealing.     

<Emphasis Type="Italic">In Situ</Emphasis> Study of Reduction Process of CuO Paste and Its Effect on Bondability of Cu-to-Cu Joints

A bonding method utilizing redox reactions of metallic oxide microparticles achieves metal-to-metal bonding in air, which can be alternative to lead-rich high-melting point solder. However, it is known that the degree of the reduction of metallic oxide microparticles have an influence on the joint strength using this bonding method. In this paper, the reduction behavior of CuO paste and its effect on Cu-to-Cu joints were investigated through simultaneous microstructure-related x-ray diffraction and differential scanning calorimetry measurements. The CuO microparticles in the paste were gradually reduced to submicron Cu₂O particles at 210–250°C. Subsequently, Cu nanoparticles were generated instantaneously at 300–315°C. There was a marked difference in the strengths of the joints formed at 300°C and 350°C. Thus, the Cu nanoparticles play a critical role in sintering-based bonding using CuO paste. Furthermore, once the Cu nanoparticles have formed, the joint strength increases with higher bonding temperature (from 350°C to 500°C) and pressure (5–15 MPa), which can exceed the strength of Pb-5Sn solder at higher temperature and pressure.     

The Melting Characteristics and Interfacial Reactions of Sn-ball/Sn-3.0Ag-0.5Cu-paste/Cu Joints During Reflow Soldering

In this work, the melting characteristics and interfacial reactions of Sn-ball/Sn-3.0Ag-0.5Cu-paste/Cu (Sn/SAC305-paste/Cu) structure joints were studied using differential scanning calorimetry, in order to gain a deeper and broader understanding of the interfacial behavior and metallurgical combination among the substrate (under-bump metallization), solder ball and solder paste in a board-level ball grid array (BGA) assembly process, which is often seen as a mixed assembly using solder balls and solder pastes. Results show that at the SAC305 melting temperature of 217°C, neither the SAC305-paste nor the Sn-ball coalesce, while an interfacial reaction occurs between the SAC305-paste and Cu. A slight increase in reflow temperature (from 217°C to 218°C) results in the coalescence of the SAC305-paste with the Sn-ball. The Sn-ball exhibits premelting behavior at reflow temperatures below its melting temperature, and the premelting direction is from the bottom to the top of the Sn-ball. Remarkably, at 227°C, which is nearly 5°C lower than the melting point of pure Sn, the Sn-ball melts completely, resulting from two eutectic reactions, i.e., the reaction between Sn and Cu and that between Sn and Ag. Furthermore, a large amount of bulk Cu₆Sn₅ phase forms in the solder due to the quick dissolution of Cu substrate when the reflow temperature is increased to 245°C. In addition, the growth of the interfacial Cu₆Sn₅ layer at the SAC305-paste/Cu interface is controlled mainly by grain boundary diffusion, while the growth of the interfacial Cu₃Sn layer is controlled mainly by bulk diffusion.     

Thermal performance of sputtered insoluble Cu(W) films for advanced barrierless metallization

The thermal performance of sputtered Cu films with dilute insoluble W (1.3 at.%) on barrierless Si substrates has been studied, using the analyses of focused ion beam, x-ray diffraction, and electrical resistivity measurement. The role of the Cu(W) film as a seed layer has been confirmed based on the thermal performance evaluations in both thermal cycling and isothermal annealing at various temperatures. The electrical resistivity of ∼1.8 μΩ-cm for Cu/Cu(W) film is obtained after thermal annealing at 400°C. Because of the good thermal stability, the Cu(W) seed layer is also considered to act as a diffusion buffer and is stable up to 490°C for the barrierless Si scheme. The results indicate that the Cu/Cu(W) scheme has potential in advanced barrierless metallization applications.     

Effect of annealing on the surface microstructural evolution and the electromigration reliability of electroplated Cu films

This paper presents the effects of annealing, performed over a temperature range from 200°C to 400°C, on the surface microstructural evolution and the electromigration reliability of electroplated Cu films. After annealing, a substantial increase in surface roughness was observed, while variations in mean grain size and nanoindentation hardness were minor. Given the annealing temperature, the surface roughness was larger for the films annealed in forming gas, due to the existence of hydrogen. In particular, the films annealed at 400°C in forming gas demonstrated severe grain-boundary grooving and surface voiding. The defective nature of the annealed surface can be alleviated by chemical-mechanical polishing (CMP), when annealing is conducted prior to the CMP. However, it appears that a sequential thermal excursion at relatively high temperatures re-aggravates the integrity of the Cu surface. This argument may be supported by the electromigration-test results on dual-damascene interconnects fabricated using two different thermal profiles. The electromigration lifetimes were longer by more than a factor of two for the interconnects that skipped a post-passivation anneal at 400°C. The experimental evidence presented in this work suggests that controlling the integrity and quality of the Cu surface is an important step in ensuring good electromigration reliability.     

Effects of barrier layer and processing conditions on thin film Cu microstructure

The crystallographic texture and grain size of sputtered Cu films were characterized as a function of deposition temperature, barrier layer material, and vacuum conditions. For Cu deposited in a HV chamber, (111) Cu texture was found to weaken with increasing deposition temperatures on W, amorphous C and Ta barrier layers, each deposited at 30°C. Conversely, under identical Cu deposition conditions, texture was found to strengthen with increasing deposition temperature on Ta deposited at 100°C. Median Cu grain size varied parabolically with deposition temperature on all barrier layers and was slightly higher on the 100°C Ta at a given Cu deposition temperature, relative to the other underlayers. For depositions in an UHV chamber, Cu texture was found to strengthen with increasing Cu deposition temperature, independent of Ta deposition temperature. Median Cu grain size, however, was still higher on 100°C Ta than on 30°C Ta. The observed differences between the two different chambers suggest that the trend of weak texture at elevated deposition temperatures may be related to contamination. Characterization of the Ta underlayers revealed that the strengthened texture of Cu films deposited on 100°C Ta is likely related to textural inheritance.     

Variable energy positron beam characterization of defects in as-grown and annealed low temperature grown GaAs

Variable energy positron annihilation measurements on as-grown and annealed GaAs grown by molecular beam epitaxy at temperatures between 230 and 350°C have been performed. Samples were subjected to either isochronal anneals to temperatures in the range 300 to 600°C or rapid thermal anneals to 700, 800, and 900°C. A significant increase in the S-parameter was observed for all samples annealed to temperatures greater than 400°C. The positron annihilation characteristics of the defect produced upon annealing are consistent with divacancies or larger vacancy clusters. The concentration of as-grown and anneal generated defects is found to decrease with increasing growth temperature.     

The structural,optical, and electrical properties of vacuum evaporated Cu-doped ZnTe polycrystalline thin films

We have studied the structural, optical, and electrical properties of thermally evaporated, Cu-doped, ZnTe thin films as a function of Cu concentration and post-deposition annealing temperature. X-ray diffraction measurements showed that the ZnTe films evaporated on room temperature substrates were characterized by an average grain size of 300Å with a (111) preferred orientation. Optical absorption measurements yielded a bandgap of 2.21 eV for undoped ZnTe. A bandgap shrinkage was observed for the Cu-doped films. The dark resistivity of the as-deposited ZnTe decreased by more than three orders of magnitude as the Cu concentration was increased from 4 to 8 at.% and decreased to less than 1 ohm-cm after annealing at 260°C. For films doped with 6–7 at.% Cu, an increase of resistivity was also observed during annealing at 150–200°C. The activation energy of the dark conductivity was measured as a function of Cu concentration and annealing temperature. Hall measurements yielded hole mobility values in the range between 0.1 and 1 cm²/V·s for both as-deposited and annealed films. Solar cells with a CdS/CdTe/ZnTe/metal structure were fabricated using Cudoped ZnTe as a back contact layer on electrodeposited CdTe. Fill factors approaching 0.75 and energy conversion efficiencies as high as 12.1% were obtained.     

Shear and Pull Testing of Sn-3.0Ag-0.5Cu Solder with Ti/Ni(V)/Cu Underbump Metallization During Aging

Ti/Ni(V)/Cu underbump metallization (UBM) is widely used in flip-chip technology today. The advantages of Ti/Ni(V)/Cu UBM are a low reaction rate with solder and the lack of a magnetic effect during sputtering. Sn atoms diffuse into the Ni(V) layer to form a Sn-rich phase, the so-called Sn-patch, during reflow and aging. In this study, the relationship between interfacial reaction and mechanical properties of the solder joints with Ti/Ni(V)/Cu UBM was evaluated. Sn-3.0Ag-0.5Cu solder was reflowed on sputtered Ti/Ni(V)/Cu UBM, and then the reflowed samples were aged at 125°C and 200°C, respectively. (Cu,Ni)₆Sn₅ was formed and grew gradually at the interface of the solder joints during aging at 125°C. The Sn-patch replaced the Ni(V) layer, and (Ni,Cu)₃Sn₄ was thus formed between (Cu,Ni)₆Sn₅ and the Sn-patch at 200°C. The Sn-patch, composed of Ni and V₂Sn₃ after reflow, was transformed to V₂Sn₃ and amorphous Sn during aging. Shear and pull tests were applied to evaluate the solder joints under various heat treatments. The shear force of the solder joints remained at 421 mN, yet the pull force decreased after aging at 125°C. Both the shear and pull forces of the solder joints decreased during aging at 200°C. The effects of aging temperature on the mechanical properties of solder joint were investigated and discussed.     

Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package

Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias.     

Low-Temperature Synthesis of High-Adhesion Cu(Mg) Alloy Films on Glass Substrates

Cu(0.5 at.%Mg) alloy films were deposited on glass substrates, and annealed at 200–400 °C in vacuum. The resistivity of the Cu(Mg) films was reduced to about 3.0 μΩcm after annealing at 200 °C for 30 min, and the tensile strength of adhesion of the Cu(Mg) films to the glass substrates was increased to 30–40 and 35–55 MPa after annealing at 250 and 300 °C, respectively. The reduction in resistivity can be explained as reduced impurity scattering and grain-boundary scattering, since Mg segregation to the film surface and Cu(Mg)/glass interface, and consequent Cu grain growth, were observed. Increased adhesion of the Cu(Mg) films to glass substrates after annealing was also explained by the strong segregation of Mg atoms, and the formation of a reaction layer at the interface. Mg atoms were observed to have reacted with the glass substrates and formed a thin crystalline MgO layer at the interface in the samples annealed at 300 °C, while Mg atoms were highly concentrated above the Cu(Mg)/glass interface without oxide formation at the interface in the samples annealed at 250 °C. Thus, the process temperature and time to obtain low-resistivity and high-adhesion Cu alloy films on glass substrates could be reduced to 250 °C and 30 min using Cu(Mg) films.     

Influence of flux on wetting behavior of lead-free solder balls during the infrared-reflow process

The effects of two different fluxes (A6 and B6) on the wetting performance of Sn-3.5Ag-0.5Cu lead-free solder balls were investigated during the reflow process. Solder ball wetting behavior in real time via an optical microscope coupled with a video recorder during the reflow process was studied. The lead-free solder balls started to melt and wet at 210°C by using A6, which is 8°C lower than the melting point (218°C) of the solder material used. The wetting performance of the lead-free solder ball was dramatically enhanced by using A6. The wettability test indicated that the height of the solder ball after the reflow process with flux A6 was significantly lower than that with B6. It was found that strong fluxing capability caused these phenomena.