Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Low-voltage-driven pentacene thin-film transistors with cross-linked poly(4-vinylphenol)/high-k Bi55b3O15 hybrid dielectric for phototransistor

This paper describes the fabrication of pentacene thin-film transistors (TFTs) with an organic/inorganic hybrid gate dielectric, consisting of cross-linked poly(4-vinylphenol) (PVP) and Bi5Nb3O15. A 300-nm-thick Bi5Nb3O15 dielectric film, grown at room temperature, exhibits a high dielectric constant (high-k) value of 40 but has an undesirable interface with organic semiconductors (OSC). To form better interfaces with OSC, a cross-linked PVP dielectric was stacked on the Bi5Nb3O15 dielectric. It is shown that, with the introduction of a hybrid dielectric, our devices not only can be operated at a low voltage (- -5 V) but also have improved electrical characteristics and photoresponse, including a field-effect mobility of 0.72 cm2/V x s, current sub-threshold slopes of 0.29 V/decade, and a photoresponse of 4.84 at a gate bias V(G) = 0 V under 100 mW/cm2 AM 1.5 illumination.     

Processing and performance of organic insulators as a gate layer in organic thin film transistors fabricated on polyethylene terephthalate substrate

Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of dielectric layer on polyethylene terephthalate (PET), characterization of dielectric property, pentacene film morphology and OTFT characterization. Here, we present the processing and performance of three organic dielectrics, poly(4-vinylphenol) (PVPh), polyvinyl alcohol (PVA) and poly(methyl methacrylate) (PMMA), as a gate layer in pentacene-based organic thin film transistor on PET substrate. We have used thermogravimetric analysis of organic dielectric solution to determine annealing temperature for spin-coated films of these dielectrics. Comparison of the leakage currents for the three dielectrics shows PVA exhibiting lowest leakage (in the voltage range of ?30 to +30 V). This is partly because solvent is completely eliminated in the case of PVA as observed by differential thermogravimetric analysis (DTGA). We propose that DTGA can be a useful tool to optimize processing of dielectric layers. From organic thin film transistor point of view, crystal structure, morphology and surface roughness of pentacene film on all the dielectric layers were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). We observe pyramidal pentacene on PVPh whereas commonly observed dendritic pentacene on PMMA and PVA surface. Pentacene morphology development is discussed in terms of surface roughness, surface energy and molecular nature of the dielectric layer.     

Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric

A self-assembled film of gold nanoparticles is integrated into the gate dielectric of an organic thin-film transistor to produce memory effects. The transistor is fabricated on a heavily doped n-type silicon (n/sup +/-Si) substrate with a thermally grown oxide layer of 100 nm thick. n/sup +/-Si serves as the gate electrode while the oxide layer functions as the gate dielectric. Gold nanoparticles as the floating gate for charge storage are deposited on the gate oxide by electrostatic layer-by-layer self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Gold nanoparticles are charged or discharged with different gate bias so that the channel conductance is modulated. The memory transistor has an on/off ratio over 1500 and data retention time of about 200 s. The low-temperature solution-based process is especially suitable for plastic-based circuits. Therefore, the results of this study could accelerate achievement of cheap and flexible organic nonvolatile memories.     

Behavior of pentacene initial nucleation on various dielectrics and its effect on carrier transport in organic field-effect transistor

The influence of dielectric surface energy on the initial nucleation and the growth of pentacene films as well as the electrical properties of the pentacene-based field-effect transistors are investigated. We have examined a range of organic and inorganic dielectrics with different surface energies, such as polycarbonate/SiO2, polystyrene/SiO2, and PMMA/SiO2 bi-layered dielectrics and also the bare SiO2 dielectric. Atomic force microscopy measurements of sub-monolayer and thick pentacene films indicated that the growth of pentacene film was in Stranski-Kranstanow growth mode on all the dielectrics. However, the initial nucleation density and the size of the first-layered pentacene islands deposited on different dielectrics are drastically influenced by the dielectric surface energy. With the increasing of the surface energy, the nucleation density increased and thus the average size of pentacene islands for the first mono-layer deposition decreased. The performance of fabricated pentacene-based thin film transistors was found to be highly related to nucleation density and the island size of deposited Pentacene film, and it had no relationship to the final particle size of the thick pentacene film. The field effect mobility of the thin film transistor could be achieved as high as 1.38 cm2Ns with on/off ratio over 3 x 10(7) on the PS/SiO2 where the lowest surface energy existed among all the dielectrics. For comparison, the values of mobility and on/off ratio were 0.42 cm2Ns and 1 x 10(6) for thin film transistor deposited directly on bare SiO2 having the highest surface energy.     

Characterization of poly(vinylidene fluoride-trifluoroethylene) 50/50 copolymer films as a gate dielectric

Thin films of poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) 50/50 copolymer were prepared by spin coating on p-Si substrate. Thermal behavior of the film was observed by measuring the film thickness with ellipsometry as a function of the temperature and abrupt volume expansion was observed at 130–150 °C. Capacitance-voltage (C-V) and current-voltage (I-V) behavior of the aluminum/P(VDF-TrFE)/p-Si MIS (metal-insulator-semiconductor) structures were studied and dielectric constant of the P(VDF-TrFE) film was measured to be about 15.3 at optimum condition. No hysteresis was observed in the C-V curve for films as deposited and annealed (70–200 °C). Films annealed at temperatures higher than the volume expansion temperature showed substantial surface roughness due to the crystallization. Flat band voltage (V_FB) of the MIS structure with as deposited films was about −0.3 V and increased up to −2.0 V with annealing. This suggested that positive charges were generated in the film. Electronic properties of the annealed P(VDF-TrFE) film at above melting temperature were degraded substantially with larger shift in flat band voltage, low dielectric constant and low breakdown voltage. Organic thin film transistor with pentacene active layer and P(VDF-TrFE) as a gate dielectric layer showed a mobility of 0.31 cm²/V·s and threshold voltage of −0.45 V.     

Cu/Al_2O_3复合薄膜的制备及其抗氧化性能

本文在纺织纤维基材表面采用二次溅射沉积法制备了Cu/Al_2O_3复合薄膜,利用扫描电镜(SEM)、X射线能谱仪(EDX)和矢量网络分析仪对室温环境下存放3600h的复合薄膜的表面形貌、元素含量以及屏蔽效能进行了测试,并与相同工艺条件下制备的纯Cu薄膜进行了对比分析。结果表明:与纯Cu薄膜结构的不稳定性相比,由于复合薄膜表层Al_2O_3薄膜的结构稳定性和致密性,Cu/Al_2O_3复合薄膜在保证高屏蔽性能的前提下,具有整体结构的稳定性,表现出了良好的抗氧化性能。     

Organic thin-film transistors using pentacene and SiOC film

Pentacene for organic thin-film transistors (OTFTs) was deposited on the SiOC film by thermal evaporation. The transfer characteristic of the pentacene channel as the active layer is dependent on the chemical properties of a surface-on-gate insulator. Hybrid-type SiOC film can have all chemical properties from organic to inorganic properties according to the deposition condition. Pentacene on SiOC film shows the gradient or normal growth because of the C=C bond in SiOC film. Normal growth of pentacene molecules increased the grain size of the surface of pentacene on SiOC film, and the mobility of OTFTs on SiOC films prepared with an O/sub 2//(BTMSM+O/sub 2/) flow rate ratio of 80% is 2.19 (cm/sup 2//V/sub s/).     

Characteristics of sputtered Al-doped ZnO films for transparent electrodes of organic thin-film transistor

Aluminum-doped ZnO (AZO) thin-films were deposited with various RF powers at room temperature by radio frequency (RF) magnetron sputtering method. The electrical properties of the AZO film were improved with the increasing RF power. These results can be explained by the improvement of the crystallinity in the AZO film. We fabricated the organic thin-film transistor (OTFT) of the bottom gate structure using pentacene active and poly-4-vinyl phenol gate dielectric layers on the indium tin oxide gate electrode, and estimated the device properties of the OTFTs including drain current-drain voltage (I_D-V_D), drain current-gate voltage (I_D-V_G), threshold voltage (V_T), on/off ratio and field effect mobility. The AZO film that grown at 160 W RF power exhibited low resistivity (1.54 × 10^− 3 Ω·cm), high crystallinity and uniform surface morphology. The pentacene thin-film transistor using the AZO film that's fabricated at 160 W RF power exhibited good device performance such as the mobility of 0.94 cm²/V s and the on/off ratio of ~ 10⁵. Consequently, the performance of the OTFT such as larger field-effect carrier mobility was determined the conductivity of the AZO source/drain (S/D) electrode. AZO films prepared at room temperature by the sputtering method are suitable for the S/D electrodes in the OTFTs.     

A comparison between bottom contact and top contact all organic field effect transistors assembled by soft lithography

All-organic Field Effect Transistors (FETs) on plastic were fabricated by means of an innovative, simple and inexpensive technique. A thin Mylar® foil acts both as substrate and gate dielectric. We used pentacene, deposited by thermal sublimation, as semiconducting layer while contacts were fabricated with poly(ethylene-dioxythiophene)/polystyrene sulfonate (PEDOT/PSS) by means of soft lithography. On the opposite side of the foil a thin PEDOT/PSS film, acting as gate electrode, was spin coated. It is worth noting that this technique allows the realization of bottom contact and top contact devices on the same substrate and with the same semiconducting layer. Furthermore, assisted by Scanning Probe Microscopy investigations, we investigated how the device structure influences its electrical properties in terms of hole mobility, Series Contact Resistance and parasitic capacitance effects. The comparison between top-contact and bottom-contact devices shows interesting marked differences that can be mainly attributed to a different quality of PEDOT/PSS-semiconductor interface. The flexibility of the obtained structure and the easy scalability of the technological process open the way for economic production of high-resolution organic devices.     

Evaluation of molecular orientation and alignment of poly(3-hexylthiophene) on Au (111) and on poly(4-vinylphenol) surfaces

The orientation and alignment of regioregular poly(3-hexylthiophene) (P3HT) molecules on Au (111) surface and on poly(4-vinylphenol) (PVP) thin film were investigated. The P3HT molecules on the smooth Au (111) are oriented with both the backbones and the side chains parallel to the substrate (plane-on orientation) as revealed by the scanning tunneling microscope (STM) images. However, the P3HT molecules on the PVP thin films are preferably oriented with side chains perpendicular to the surface (edge-on orientation). Surface modification of the PVP by hexamethyldisilazane (HMDS) can increase the crystalline size in the P3HT semicrystalline films. The performance of an all-polymer organic field-effect transistor (OFET) with the drop-cast P3HT semiconductor layer and the crosslinked PVP gate insulator on poly(ethylene naphthalate) (PEN) substrate was evaluated.     

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Abstract

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc₆) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO₂) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10^?2 cm² V^?1 s^?1 and 10⁶ for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.     

Enhanced ferroelectric properties of multilayer SrBi2Ta2O9/SrBi2Nb2O9 thin films for NVRAM applications

Ferroelectric SrBi₂Ta₂O₉/SrBi₂Nb₂O₉ (SBT/SBN) multilayer thin films with various stacking periodicity were deposited on Pt/TiO₂/SiO₂/Si substrate by pulsed laser deposition technique. The X-ray diffraction patterns indicated that the perovskite phase was fully formed with polycrystalline structure in all the films. The Raman spectra showed the frequency of the O–Ta–O stretching mode for multilayer and single layer SrBi₂(Ta_0.5Nb_0.5)₂O₉ (SBNT) samples was 827–829 cm⁻¹, which was in between the stretching mode frequency in SBT (813 cm⁻¹) and SBN (834 cm⁻¹) thin films. The dielectric constant was increased from 300 (SBT) to 373 at 100 kHz in the double layer SBT/SBN sample with thickness of each layer being 200 nm. The remanent polarization (2P_r) for this film was obtained 41.7 μC/cm², which is much higher, compared to pure SBT film (19.2 μC/cm²). The coercive field of this double layer film (67 kV/cm) was found to be lower than SBN film (98 kV/cm).     

Characteristics of nanocomposite ZrO2/Al2O3 films deposited by plasma-enhanced atomic layer deposition

Nanocomposite ZrO2/Al2O3 (ZAO) films were deposited on Si by plasma-enhanced atomic layer deposition and the film characteristics including interfacial oxide formation, dielectric constant (k), and electrical breakdown strength were investigated without post-annealing process. In both the mixed and nano-laminated ZAO films, the thickness of the interfacial oxide layer (T(IL)) was considerably reduced compared to ZrO2 and Al2O3 films. The T(IL) was 0.8 nm in nano-composite films prepared at a mixing ratio (ZrO2:Al2O3) of 1:1. The breakdown strength and the leakage current level were greatly improved by adding Al2O3 as little as 7.9% compared to that of ZrO2 and were enhanced more with increasing content of Al2O3. The k of ZrO2 and mixed ZAO (Al2O3 7.9%) films were 20.0 and 16.5, respectively. These results indicate that the addition of Al2O3 to ZrO2 greatly improves the electrical properties with less cost of k compared to the addition of SiO2.     

Charge-trapping characteristics of Al2O3/Cu/Al2O3 nanolaminate structures prepared through atomic layer deposition

The nanolaminate Al2O3/Cu/Al2O3 structures were constructed on p-type Si (001) substrates using atomic layer deposition (ALD) process with the aim to fabricating nonvolatile charge-trap memories. Low temperature Cu thin layers were deposited through plasma-enhanced atomic layre depositon of Cu aminoalkoxide (Cu(dmamb)2) combined with hydrogen plasma and Al2O3 layers were prepared by thermal atomic layer deposition of trimethylaluminum (TMA) combined with H2O. Nonvolatile features were confirmed using capacitance-voltage (C-V) measurements. The copper film functions as a charge-trapping layer and the Al2O3 thin layers were employed as tunneling and control oxide layers. Line shapes and binding energies of Cu metal and the thin layer of 6 nm Cu in nanolaminate structures were observed in the X-ray photoelectron spectroscopy (XPS) and high resolution transmission electron microscopy (TEM) image. The V(FB) shift width of the Al2O3 (28 nm)/Cu (6 nm)/Al2O3 (4.2 nm)/Si laminate structure is found to be 4.75 V in voltage sweeping between -10 and +10 V, leading to the trap density of 1.68 x 10(18) cm(-3).     

High-performance low-voltage organic field-effect transistors prepared on electro-polished aluminum wires

We report the preparation of high-performance low-voltage pentacene-based organic field-effect transistors (OFETs) fabricated on a metallic fiber (Al wire) substrate. The surface roughness of the wire was significantly reduced after 10 min of electro-polishing. A 120 nm thick Al(2)O(3) gate dielectric layer was deposited on the anodized wire, followed by octadecyltrichlorosilane (ODTS) treatment. The ODTS-modified Al(2)O(3) gate dielectrics formed around the Al wire showed a high capacitance of 50.1 nF cm(-2) and hydrophobic surface characteristics. The resulting OFETs exhibited hysteresis-free operation with a high mobility of 0.345 cm(2) V(-1) s(-1) within a low operating voltage range of -5 V, and maintained their high performance at an applied tensile strain of bending radius ~2.2.     

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc₆) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO₂) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10⁻² cm² V⁻¹ s⁻¹ and 10⁶ for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.     

Fabrication and optical properties of Pb(Mg(1/3)Nb(2/3))O(3)-PbTiO(3) thin films on Si substrates using the PLD method.

Epitaxial 0.67Pb(Mg(1/3)Nb(2/3))O(3)-PbTiO(3)-0.33PbTiO(3) (PMN-PT) thin films with electro-optic effects were fabricated on (PMN-PT) thin films with electro-optic effects were fabricated on (La0(0.5)Sr0(0.5))CoO(3) (LSCO)/CeO(2)/YSZ-buffered Si(001) substrates using double-pulse excitation pulsed laser deposition (PLD) method with a mask placed between the target and the substrate. Epitaxial growth of PMN-PT thin films was undertaken using the two-step growth method of PMN-PT film. The PMN-PT seed layer was deposited at 500 degrees C on the LSCO/CeO(2)/YSZ/Si, which temperature was the same as that used for LSCO deposition. The PMN-PT thin films were deposited on the PMN-PT seed layer at 600 degrees C, which enables growth of high-crystallinity PMN-PT films with smooth surfaces. We obtained optimum fabrication conditions of PMNPT film with micrometer-order thickness. Resultant films showed high crystallinity with full width at half maximum (FWHM) = 0.73 deg and 1.6 mum thickness. Electro-optic properties and the refractive index value were measured at 633 nm wavelength using the prism coupling method. The obtained refractive index was 2.59. The electro-optic coefficients r(13) and r(33) were determined by applying the electrical field between a semitransparent, thin top electrode of Pt and a bottom LSCO electrode. The electro-optic coefficient was r(13) = 17 pm/V at transverse electric field (TE) mode and r(33) = 55 pm/V at transverse magnetic field (TM) mode.     

Electrical characteristics of poly(3-hexylthiophene) organic thin film transistor with electroplated metal gate electrodes on polyimide

The electroplating of the gate electrode on a flexible polyimide (PI) substrate was successfully applied to the fabrication of inverted-staggered poly(3-hexylthiophene) (P3HT) organic thin film transistors (OTFTs). The Ni gate electrode was electroplated through patterned negative photo-resist (KMPR) masks onto Cu (seed)/Cr (adhesion) layers that had been sputter-deposited on O₂-plasma-treated PI substrates. The electrical measurements of the fabricated OTFTs with the SiO₂ gate insulator indicated non-ideal output characteristics, which are similar to the model of electrical transport by a space-charge limited current (SCLC). The use of a poly(4-vinyl phenol) (PVP) and SiO₂/PVP bilayer gate dielectric produced output characteristics that were closer to the ideal TFT behavior but led to a lower effective mobility and on/off current (I_on/I_off).     

Al预沉积层对金属有机物化学气相沉积方法在Si衬底上生长AlN缓冲层和GaN外延层的影响

采用金属有机物化学气相沉积法(MOCVD)在硅(Si)衬底制备铝/氮化铝/氮化镓(Al/AlN/GaN)多层薄膜,使用光学显微镜(OM)、原子力显微镜(AFM)、X射线衍射(XRD)等手段表征AlN和GaN薄膜的微观结构和晶体质量,研究了TMAl流量对AlN薄膜和GaN薄膜的形核和生长机制的影响。结果表明,预沉积Al层能促进AlN的形核和生长,进而提高GaN外延层的薄膜质量。TMAl流量太低则预沉积Al层不充分,AlN缓冲层的质量取决于由形核长大的高结晶度AlN薄膜与在气氛中团聚长大并沉积的低结晶度AlN薄膜之间的竞争,AlN薄膜的质量随着TMAl流量的升高而提高,GaN薄膜的质量也随之提高。TMAl流量太高则预沉积Al层过厚,AlN缓冲层的质量取决于由形核长大的高结晶度AlN薄膜与Al-Si回融蚀刻之间的竞争,AlN薄膜的质量随着TMAl流量的升高而降低,GaN薄膜的质量也随之降低。