In-Memory Computing with Memristor Content Addressable Memories for Pattern Matching

The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in-memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.     

Compact Two‐State‐Variable Second‐Order Memristor Model

A key requirement for using memristors in functional circuits is a predictive physical model to capture the resistive switching behavior, which shall be compact enough to be implemented using a circuit simulator. Although a number of memristor models have been developed, most of these models (i.e., first‐order memristor models) have utilized only a one‐state‐variable. However, such simplification is not adequate for accurate modeling because multiple mechanisms are involved in resistive switching. Here, a two‐state‐variable based second‐order memristor model is presented, which considers the axial drift of the charged vacancies in an applied electric field and the radial vacancy motion caused by the thermophoresis and diffusion. In particular, this model emulates the details of the intrinsic short‐term dynamics, such as decay and temporal heat summation, and therefore, it accurately predicts the resistive switching characteristics for both DC and AC input signals.     

A ferroelectric capacitor macromodel and parameterization algorithmfor SPICE simulation

A compact equivalent circuit model, or macromodel, is presented which reproduces both the DC charge storage and transient switching current responses of a ferroelectric capacitor. The macromodel circuit element values are rigorously linked to physical quantities which are readily characterized with simple electrical measurements. A software package is described which both parameterizes and optimizes the model to measured data and outputs a SPICE input file. Together, the macromodel and parameterization software form a complete linkage between material characterization and circuit design which is largely transparent to the design engineer. Optimization results lend insight into the underlying theory of ferroelectric switching and the sources of nonideal charge storage. SPICE simulations demonstrate the utility of the macromodel for VLSI circuit simulation     

Vacancy‐Induced Synaptic Behavior in 2D WS2 Nanosheet–Based Memristor for Low‐Power Neuromorphic Computing

Memristors with nonvolatile memory characteristics have been expected to open a new era for neuromorphic computing and digital logic. However, existing memristor devices based on oxygen vacancy or metal‐ion conductive filament mechanisms generally have large operating currents, which are difficult to meet low‐power consumption requirements. Therefore, it is very necessary to develop new materials to realize memristor devices that are different from the mechanisms of oxygen vacancy or metal‐ion conductive filaments to realize low‐power operation. Herein, high‐performance and low‐power consumption memristors based on 2D WS₂ with 2H phase are demonstrated, which show fast ON (OFF) switching times of 13 ns (14 ns), low program current of 1 µA in the ON state, and SET (RESET) energy reaching the level of femtojoules. Moreover, the memristor can mimic basic biological synaptic functions. Importantly, it is proposed that the generation of sulfur and tungsten vacancies and electron hopping between vacancies are dominantly responsible for the resistance switching performance. Density functional theory calculations show that the defect states formed by sulfur and tungsten vacancies are at deep levels, which prevent charge leakage and facilitate the realization of low‐power consumption for neuromorphic computing application.     

Truly Concomitant and Independently Expressed Short‐ and Long‐Term Plasticity in a Bi2O2Se‐Based Three‐Terminal Memristor

Concomitance of diverse synaptic plasticity across different timescales produces complex cognitive processes. To achieve comparable cognitive complexity in memristive neuromorphic systems, devices that are capable of emulating short‐term (STP) and long‐term plasticity (LTP) concomitantly are essential. In existing memristors, however, STP and LTP can only be induced selectively because of the inability to be decoupled using different loci and mechanisms. In this work, the first demonstration of truly concomitant STP and LTP is reported in a three‐terminal memristor that uses independent physical phenomena to represent each form of plasticity. The emerging layered material Bi₂O₂Se is used for memristors for the first time, opening up the prospects for ultrathin, high‐speed, and low‐power neuromorphic devices. The concerted action of STP and LTP allows full‐range modulation of the transient synaptic efficacy, from depression to facilitation, by stimulus frequency or intensity, providing a versatile device platform for neuromorphic function implementation. A heuristic recurrent neural circuitry model is developed to simulate the intricate “sleep–wake cycle autoregulation” process, in which the concomitance of STP and LTP is posited as a key factor in enabling this neural homeostasis. This work sheds new light on the development of generic memristor platforms for highly dynamic neuromorphic computing.     

Internal ion transport in ionic 2D CuInP2S6 enabling multi-state neuromorphic computing with low operation current

Memristor-based neuromorphic computing is promising for artificial intelligence. However, most of the reported memristors have limited linear computing states and consume large operation energy which hinder their applications. Herein, we report a memristor based on ionic two-dimensional CuInP₂S₆ (2D CIPS), in which up to 1350 linear conductance states are achieved by controlling the migration of internal Cu ions in CIPS. In addition, the device shows a low operation current of ∼100 pA. Cu ions are proven to move along the electric field by in-situ scanning electron microscopy and energy dispersive spectroscopy measurements. Furthermore, complex signal transport among multiple neurons in the brain is imitated by 2D CIPS-based memristor arrays. Our results offer a new platform to fabricate high-performance memristors based on ion transport in 2D materials for neuromorphic computing.     

Self-assembly-induced formation of high-density silicon oxide memristor nanostructures on graphene and metal electrodes

We report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by a block copolymer self-assembly process. Optimized surface functionalization provides stacking structures of Si-containing block copolymer thin films to generate uniform memristor device structures. Both the silicon oxide film and nanodot memristors, which were formed by the plasma oxidation of the self-assembled block copolymer thin films, presented unipolar switching behaviors with appropriate set and reset voltages for resistive memory applications. This approach offers a very convenient pathway to fabricate ultrahigh-density resistive memory devices without relying on high-cost lithography and pattern-transfer processes.     

A Low-Current and Analog Memristor with Ru as Mobile Species

The switching parameters and device performance of memristors are predominately determined by their mobile species and matrix materials. Devices with oxygen or oxygen vacancies as the mobile species usually exhibit a great retention but also need a relatively high switching current (e.g., >30 µA), while devices with Ag or Cu as cation mobile species do not require a high switching current but usually show a poor retention. Here, Ru is studied as a new type of mobile species for memristors to achieve low switching current, fast speed, good reliability, scalability, and analog switching property simultaneously. An electrochemical metallization-like memristor with a stack of Pt/Ta₂O₅/Ru is developed. Migration of Ru ions is revealed by energy-dispersive X-ray spectroscopy mapping and in situ transmission electron microscopy within a sub-10 nm active device area before and after switching. The results open up a new avenue to engineer memristors for desired properties.     

Gate‐Tunable and Multidirection‐Switchable Memristive Phenomena in a Van Der Waals Ferroelectric

Memristive devices have been extensively demonstrated for applications in nonvolatile memory, computer logic, and biological synapses. Precise control of the conducting paths associated with the resistance switching in memristive devices is critical for optimizing their performances including ON/OFF ratios. Here, gate tunability and multidirectional switching can be implemented in memristors for modulating the conducting paths using hexagonal α‐In₂Se₃, a semiconducting van der Waals ferroelectric material. The planar memristor based on in‐plane (IP) polarization of α‐In₂Se₃ exhibits a pronounced switchable photocurrent, as well as gate tunability of the channel conductance, ferroelectric polarization, and resistance‐switching ratio. The integration of vertical α‐In₂Se₃ memristors based on out‐of‐plane (OOP) polarization is demonstrated with a device density of 7.1 × 10⁹ in.^?2 and a resistance‐switching ratio of well over 10³. A multidirectionally operated α‐In₂Se₃ memristor is also proposed, enabling the control of the OOP (or IP) resistance state directly by an IP (or OOP) programming pulse, which has not been achieved in other reported memristors. The remarkable behavior and diverse functionalities of these ferroelectric α‐In₂Se₃ memristors suggest opportunities for future logic circuits and complex neuromorphic computing.     

Influence of Geometry on the Memristive Behavior of the Domain Wall Spintronic Memristors and Its Applications for Measurement

A memristor is characterized by its electrical memory resistance (memristance), which is a function of the historic profile of the applied current (voltage). This unique ability allows reducing charge- and flux-based measurements to straightforward resistance measurements. The memristive measurement seeks a memristor with a constant modulation of the memristance (memductance) with respect to the charge (flux) for charge (flux)-based measurements. In this work the geometry dependent memristive behavior of a spintronic device is studied to demonstrate the possibility of both charge- and flux-based sensing, using spintronic memristors with different device geometries. The dynamic properties of a propagating magnetic domain wall in different geometrical structures make the spintronic memristor suitable for the charge-based capacitance and flux-based inductance measurements.     

Environmentally Robust Memristor Enabled by Lead‐Free Double Perovskite for High‐Performance Information Storage

Memristors are emerging as a rising star of new computing and information storage techniques. However, the practical applications are severely challenged by their instability toward harsh conditions, including high moisture, high temperatures, fire, ionizing irradiation, and mechanical bending. In this work, for the first time, lead‐free double perovskite Cs₂AgBiBr₆ is utilized for environmentally robust memristors, enabling highly efficient information storage. The memory performance of the typical indium‐tin‐oxide/Cs₂AgBiBr₆/Au sandwich‐like memristors is retained after 1000 switching cycles, 10⁵ s of reading, and 10⁴ times of mechanical bending, comparable to other halide perovskite memristors. Most importantly, the memristive behavior remains robust in harsh environments, including humidity up to 80%, temperatures as high as 453 K, an alcohol burner flame for 10 s, and ⁶⁰Co γ‐ray irradiation for a dosage of 5 × 10⁵ rad (SI), which is not achieved by any other memristors and commercial flash memory techniques. The realization of an environmentally robust memristor from Cs₂AgBiBr₆ with a high memory performance will inspire further development of robust electronics using lead‐free double perovskites.     

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.     

Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine

Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small‐scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High‐precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single‐layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible.     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

基于电化学金属化机制的电子突触电导可控性研究进展

随着数据信息的爆炸性增长和微电子加工工艺逼近物理极限,互补金属氧化物半导体(CMOS)器件难以应用于大规模神经形态器件的构建。采用非CMOS器件实现突触可塑性模拟被认为是后摩尔时代构造人工神经网络的关键。在众多的非CMOS器件中,忆阻器具有电导可调、结构简单等优点,被认为是再现神经突触功能、实现计算存储一体化的基础元件。在众多类型的忆阻器中,基于电化学金属化机制(ECM)的忆阻器具有机理明确、可超高密度集成、对材料属性不敏感等优点,特别适合应用于电子突触的构建。但ECM电子突触存在着电导可控性不足的问题,制约着高性能神经形态器件的实现。国内外研究人员针对ECM电子突触的电导可控性展开了大量研究。本综述从器件结构和材料角度梳理了ECM电子突触电导可控性的优化方法。     

Flexible memristors as electronic synapses for neuro-inspired computation based on scotch tape-exfoliated mica substrates

Flexible memristor devices based on plastic substrates have attracted considerable attention due to their applications in wearable computers and integrated circuits. However, most plastic-substrate memristors cannot function or be grown in high-temperature environments. In this study, scotch-tape-exfoliated mica was used as the flexible memristor substrate in order to resolve these high-temperature issues. Our TiN/ZHO/IGZO memristor, which was constructed using a thin (10 μm) mica substrate, has superior flexibility and thermostability. After bending it 103 times, the device continues to exhibit exceptional electrical characteristics. It can also be implemented for transitions between high and low resistance states, even in temperatures of up to 300 °C. More importantly, the biological synaptic characteristics of paired-pulse facilitation/depression (PPF/PPD) and spike-timing-dependent plasticity (STDP) were observed through applying different pulse measurement modes. This work demonstrates that flexible memristor devices on mica substrates may potentially allow for the realization of high-temperature memristor applications for biologically-inspired computing systems.

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A two-step methodology for CMOS VLSI reliability improvement: Step one

Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck-at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two-step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre-SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.     

The effect of the memristor electrode material on its resistance to degradation under conditions of cyclic switching

The stability of titanium oxide memristors with gold and platinum electrodes with respect to switching-induced degradation has been studied. It is established that the use of gold instead of platinum as the electrode material significantly increases the resistance of a memristor to degradation in the course of repeated resistance read-write(erase) cycles. The first Russian high-endurance memristor based on titanium oxide has been obtained, which can withstand up to 3000 resistive switching cycles.     

Emerging Memristive Artificial Synapses and Neurons for Energy-Efficient Neuromorphic Computing

Memristors have recently attracted significant interest due to their applicability as promising building blocks of neuromorphic computing and electronic systems. The dynamic reconfiguration of memristors, which is based on the history of applied electrical stimuli, can mimic both essential analog synaptic and neuronal functionalities. These can be utilized as the node and terminal devices in an artificial neural network. Consequently, the ability to understand, control, and utilize fundamental switching principles and various types of device architectures of the memristor is necessary for achieving memristor-based neuromorphic hardware systems. Herein, a wide range of memristors and memristive-related devices for artificial synapses and neurons is highlighted. The device structures, switching principles, and the applications of essential synaptic and neuronal functionalities are sequentially presented. Moreover, recent advances in memristive artificial neural networks and their hardware implementations are introduced along with an overview of the various learning algorithms. Finally, the main challenges of the memristive synapses and neurons toward high-performance and energy-efficient neuromorphic computing are briefly discussed. This progress report aims to be an insightful guide for the research on memristors and neuromorphic-based computing.     

Nanocomputing by field-coupled nanomagnets

Demonstrates through simulations the feasibility of using magnetically coupled nanometer-scale ferromagnetic dots for digital information processing. Microelectronic circuits provide the input and output of the magnetic nanostructure, but the signal is processed via magnetic dot-dot interactions. Logic functions can be defined by the proper placements of dots. We introduce a SPICE macromodel of interacting nanomagnets and use this tool to design and simulate the proposed nanomagnet logic units. This SPICE model allows us to simulate such magnetic information processing devices within the same framework as conventional electronic circuits.