Study of carbon nanotube field effect transistors performance based on changes in gate parameters

Carbon nanotubes are known as an interesting material to be used in the next generations of electronic technology, especially at nano regime. Nowadays, carbon nanotube field effect transistor or CNTFET is one of the promising devices for future electronic applications. A CNTFET which uses carbon nanotube as channel or source/drain region is the most promising candidate for replacing the current silicon transistor technology. The study of modern manufacturing approach and impact of device parameters on its performance is one of the important research fields in nanoelectronics. In this paper we study some aspects of changes in gate parameters at different channel diameters. This paper shows that for small values of diameter, increasing the dielectric constant of gate insulator doesn't help to improve the performance as value of dielectric constant of gate insulator reaches a certain amount. Also, increasing the oxide thickness of gate insulator doesn't always decrease transistor performance. For high diameter values, increasing the thickness up to a certain value improves the transistor performance.     

Graphene-like metal-on-silicon field-effect transistor

This paper presents a field-effect transistor with a channel consisting of a two-dimensional electron gas located at the interface between an ultrathin metallic film of Ni and a p-type Si(111) substrate. The gate length is L = 2 μm, its width is W = 180 μm, and the source-drain separation is 188 μm, the role of the gate dielectric being played by the surface states of the ultrathin metal layer. We have demonstrated that the two-dimensional electron gas channel is modulated by the gate voltage. The dependence of the drain current on the drain voltage has no saturation region, similar to a field-effect transistor based on graphene. The drain current is 2 mA at a drain voltage of 3 V and a gate voltage of 1.07 V, while the transconductance is 0.6 mS for a drain voltage of 6 V and a gate voltage of 1 V. However, the transport in this transistor is not ambipolar, as in graphene, but unipolar.     

The geometrical effect of single walled carbon nanotube network transistors on low frequency noise characteristics

The noise characteristics of randomly networked single walled carbon nanotubes grown directly by plasma enhanced chemical vapor deposition with field effect transistor. Geometrical complexity due to the large number of tube-tube junctions in the nanotube network is expected to be one of the key factors for the noise power of 1/f dependence. We investigated low frequency noise as a function of channel length (2-10 microm) and found that increased with longer channel length. Percolational behaviors of nanotube network that differs from ordinary semiconducting and metallic materials can be characterized by a geometrical picture with electrical homo- and hetero-junctions. Fixed nanotube density provides a test conditions to evaluate the contributions of junctions as a noise center. Hooge's empirical law is applied to investigate the low frequency noise characteristics of single walled carbon nanotube random network transistors. The noise power shows the dependence of the transistor channel length. It is understood that nanotube/nanotube junctions act as a noise center. However, the differences induced by channel length in the noise power are observed as not so significant. We conclude that tolerance of low frequency noise is important property for SWNT networks as an electronic device application.     

A study on the electrical properties of plasma nitrided oxide gate dielectric in flash memory

In this paper, we address the effect of plasma nitridation on the gate dielectric in terms of device characteristics of an NMOS/PMOS transistor. Firstly, boron segregation due to plasma nitridation near Si/SiO₂ interface and bulk Si is experimentally characterised by 1D SIMS, and its profile is reproduced in simulation of which parameters for boron diffusion are accurately calibrated through a comprehensive calibration process. Secondly, the electrical behaviour of NMOS/PMOS transistor with plasma nitride gate dielectric is verified, observing uncommon behaviour of C-V diagram in the case of buried-channel PMOS transistor. We prove that an excessive amount of interface traps generated by plasma nitridation influence abnormal electrical behaviour of the NMOS/PMOS transistor.     

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.     

Electrostatic control of ions and molecules in nanofluidic transistors

We report a nanofluidic transistor based on a metal-oxide-solution (MOSol) system that is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET). Using a combination of fluorescence and electrical measurements, we demonstrate that gate voltage modulates the concentration of ions and molecules in the channel and controls the ionic conductance. Our results illustrate the efficacy of field-effect control in nanofluidics, which could have broad implications on integrated nanofluidic circuits for manipulation of ions and biomolecules in sub-femtoliter volumes.     

A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics

We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors.     

The impact of non-uniform channel layer growth on device characteristics in state of the Art Si/SiGe/Si p-metal oxide semiconductor field effect transistors

In this study we have highlighted the effect of non-uniform channel layer growth by the direct correlation of the microstructure and electrical characteristics in state-of-the-art pseudomorphic Si/SiGe p-channel metal oxide semiconductor field effect transistor devices fabricated on Si. Two nominally identical sets of devices from adjacent locations of the same wafer were found to have radically different distributions in gate threshold voltages. Due to the close proximity and narrow gate length of the devices, focused ion beam milling was used to prepare a number of thin cross-sections from each of the two regions for subsequent analysis using transmission electron microscopy. It was found that devices from the region giving a very narrow range of gate threshold voltages exhibited a uniform microstructure in general agreement with the intended growth parameters. However, in the second region, which showed a large spread in the gate threshold voltages, profound anomalies in the microstructure were observed. These anomalies consisted of fluctuations in the quality and thickness of the SiGe strained layers. The non-uniform growth of the strained SiGe layer clearly accounted for the poorly controlled threshold voltages of these devices. The results emphasize the importance of good layer growth uniformity to ensure optimum device yield.     

Ferroelectric gated electrical transport in CdS nanotetrapods

Complex nanostructures such as branched semiconductor nanotetrapods are promising building blocks for next-generation nanoelectronics. Here we report on the electrical transport properties of individual CdS tetrapods in a field effect transistor (FET) configuration with a ferroelectric Ba(0.7)Sr(0.3)TiO(3) film as high-k, switchable gate dielectric. A cryogenic four-probe scanning tunneling microscopy (STM) is used to probe the electrical transport through individual nanotetrapods at different temperatures. A p-type field effect is observed at room temperature, owing to the enhanced gate capacitance coupling. And the reversible remnant polarization of the ferroelectric gate dielectric leads to a well-defined nonvolatile memory effect. The field effect is shown to originate from the channel tuning in the arm/core/arm junctions of nanotetrapods. At low temperature (8.5 K), the nanotetrapod devices exhibit a ferroelectric-modulated single-electron transistor (SET) behavior. The results illustrate how the characteristics of a ferroelectric such as switchable polarization and high dielectric constant can be exploited to control the functionality of individual three-dimensional nanoarchitectures.     

Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowering, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire FinFETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.     

Ballistic quantum transport in nanoscale Schottky-barrier tunnel transistors

The device characteristics of the nanoscale Schottky-barrier tunnel transistor (SBTT) are investigated by solving the self-consistent two-dimensional Poisson-Schrodinger equations and treating the ballistic transport with the nonequilibrium Green's function formalism. A main focus lies in the assessment of the device performance of the SBTT as the channel length is gradually reduced down to a few nanometers. Due to the assumed ballistic transport, the device characteristics are almost the same if the channel length is greater than about 20 nm, but the device performance starts to degrade below L=20 nm. By examining the device performance in terms of the voltage gain, transfer characteristics, and the threshold voltage behavior, we suggest that the channel length of the SBTT can be reduced to approximately 10 nm. Discussions on how scattering affects the simulation results and how to control on- and off-currents by varying the Schottky-barrier height and the gate dielectric constant are also presented.     

Electrostatics of nanowire transistors

The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show that charge density on the nanowire is a sensitive function of the contact geometry. For a nanowire transistor with large gate underlaps, charge transferred from bulk electrodes can effectively "dope" the intrinsic, ungated region and allow the transistor to operate. Reducing the gate oxide thickness and the source/drain contact size decreases the length by which the source/drain electric field penetrates into the channel, thereby, improving the transistor characteristics.     

Retention characteristics of Schottky barrier tunneling transistor-nano floating gate memory with various side walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.     

Nonvolatile memory characteristics of solution-processed oxide thin-film transistors using Ag nanoparticles

We developed a nonvolatile memory device based on a solution-processed oxide thin-film transistor (TFT) with Ag nanoparticles (NPs) as the charge trapping layer. We fabricated the device using a soluble MgInZnO active channel on a SiO₂ gate dielectric, Ag NPs as a charge trapping site at the gate insulator-channel interface, and Al for source and drain electrodes.The transfer characteristics of the device showed a high level of clockwise hysteresis that can be used to demonstrate its memory function, due to electron trapping in the Ag NPs charge trapping layer. A large memory window (?V_th) was observed with a forward and backward gate voltage sweep, and this memory window was increased in size by increasing the gate voltage sweep. These results show the potential application of memory on displays and disposable electronics.     

Simulation study on a new dual-material nanowire MOS surrounding-gate transistor

In this paper, a novel field effect nanowire MOS transistor taking advantage of both dual-material gate and surrounding gate is proposed and performance characteristics are demonstrated numerically in detail. Surrounding-gate transistor is known to be used to enhance the electrostatic control of the channel, and dual-material-gate structure is extended from split-gate field effect transistor to obtain larger current and better short-channel performance. Three dimensional device simulations with Sentaurus Device are performed on this dual-material surrounding-gate transistor. Higher driving current, high ION/IOFF ratio and suppressed short-channel effects are obtained with this novel device structure.     

Fabrication of crossed junctions of semiconducting and metallic carbon nanotubes: a CNT-gated CNT-FET

We have developed a method to fabricate crossed junctions between semiconducting (s) and metallic (m) carbon nanotubes (CNTs) combining electric field directed chemical vapor deposition growth and dielectrophoretic alignment. By separating the s- and m-CNTs with a thin dielectric an ultra-small field effect transistor (FET) was fabricated. By using the m-CNT as a gate it was possible to modulate the source-drain current through the s-CNT FET channel. We have also used the m-CNT as an electrical lead. An off-state current lowering was observed when the m-CNT lead was used as a drain electrode.     

A quantum mechanical transport approach to simulation of quadruple gate silicon nanowire transistor

In this paper we have used quantum mechanical transport approach to analyse electrical characteristics of silicon nanowire transistor and have compared the results with those obtained using semi classical Boltzmann transport model. The analyse employs a three dimensional simulation of Silicon nanowire transistor based on self consistent solution of Poisson, Schrodinger equations. Quantum mechanical transport model uses the non equilibrium Green's function (NEGF) while the semi classic model doesn't account for tunneling current. The results have shown that Quantum tunneling is significant in inversion condition especially when the channel length is short. For the long devices quantum modeling and semi classical model produce the same result, and tunneling is negligible.     

单壁碳纳米管作沟道的场效应晶体管输运特性理论研究

为研究以单壁碳纳米管(CNT)作沟道的场效应晶体管(FET)的输运特性,采用非平衡格林函数(NEGF)理论,构建了CNTFET的电子输运模型,该方法摒弃粗糙的连续体模型,可实现CNTFET输运性质与手性指数的直接对接。以(17,0)锯齿型管为例,数值计算了CNTFET输出特性、转移特性、跨导、亚阈值摆幅、开关态电流比等电学特性;在等效栅氧化层厚度相同的情况下,对比了采用不同栅介质材料时上述电学特性在数值上的差异,发现随栅介质介电常数的增加,漏感应势垒降低效应变得显著,这不但导致开态时从源注入到漏的电子浓度增加、电流增大,也导致关态电流增大,开关态的电流比减少。研究还发现在通常的栅源和漏源电压下,沟道中出现热电子。     

Electrical transport of bottom-up grown single-crystal Si(1-x)Ge(x) nanowire

In this work, we fabricated an Si(1-x)Ge(x) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) by using bottom-up grown single-crystal Si(1-x)Ge(x) NWs integrated with HfO(2) gate dielectric, TaN/Ta gate electrode and Pd Schottky source/drain electrodes, and investigated the electrical transport properties of Si(1-x)Ge(x) NWs. It is found that both undoped and phosphorus-doped Si(1-x)Ge(x) NW MOSFETs exhibit p-MOS operation while enhanced performance of higher I(on)～100?nA and I(on)/I(off)～10(5) are achieved from phosphorus-doped Si(1-x)Ge(x) NWs, which can be attributed to the reduction of the effective Schottky barrier height (SBH). Further improvement in gate control with a subthreshold slope of 142?mV?dec(-1) was obtained by reducing HfO(2) gate dielectric thickness. A comprehensive study on SBH between the Si(1-x)Ge(x) NW channel and Pd source/drain shows that a doped Si(1-x)Ge(x) NW has a lower effective SBH due to a thinner depletion width at the junction and the gate oxide thickness has negligible effect on effective SBH.     

Electrical actuation and readout in a nanoelectromechanical resonator based on a laterally suspended zinc oxide nanowire

In this paper, we present experimental results describing enhanced readout of the vibratory response of a doubly clamped zinc oxide (ZnO) nanowire employing a purely electrical actuation and detection scheme. The measured response suggests that the piezoelectric and semiconducting properties of ZnO effectively enhance the motional current for electromechanical transduction. For a doubly clamped ZnO nanowire resonator with radius ~10 nm and length ~1.91 μm, a resonant frequency around 21.4 MHz is observed with a quality factor (Q) of ~358 in vacuum. A comparison with the Q obtained in air (~242) shows that these nano-scale devices may be operated in fluid as viscous damping is less significant at these length scales. Additionally, the suspended nanowire bridges show field effect transistor (FET) characteristics when the underlying silicon substrate is used as a gate electrode or using a lithographically patterned in-plane gate electrode. Moreover, the Young's modulus of ZnO nanowires is extracted from a static bending test performed on a nanowire cantilever using an AFM and the value is compared to that obtained from resonant frequency measurements of electrically addressed clamped–clamped beam nanowire resonators.