The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

DC and high-frequency device characteristics of In_0.7Ga_0.3As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I_on) gam of 20% is observed in the In_0.7Ga_0.3As QWFET over the strained Si nMOSFET at (V_g - V_t) = 0.3 V, V_ds = 0.5 V, and matched I_off, despite higher external resistance and large gate-to-channel thickness. To understand the gain in I_on, the effective carrier velocities (v_eff) near the source-end are extracted and it is observed that at constant (V_g - V_t) = 0.3 V and V_ds = 0.5 V, the v_eff of In_0.7Ga_0.3As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of v_eff and charge density (n_s), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In_0.7Ga_0.3As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher v_eff will result in more than 80% I_on increase over strained Si nMOSFETs at V_ds = 0.5 V, (V_g - V_t) = 0.3 V, and matched I_off, thus showing promise for future high-speed and low-power logic applications.     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

n-MOSFET With Silicon–Carbon Source/Drain for Enhancement of Carrier Transport

A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si_1-yC_y) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of Si_1-yC_y in the S/D regions. The carbon mole fraction incorporated is 0.013. Lattice mismatch of ~0.56% between Si _0.987C_0.013 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron-mobility enhancement. The conduction-band offset DeltaE_c between the Si_0.987 C_0.013 source and the strained Si channel could also contribute to an increased electron injection velocity nu_inj from the source. Implementation of the Si_0.987 C_0.013 S/D regions for n-MOSFET provides significant drive current I_Dsat enhancement of up to 50% at a gate length of 50 nm     

In-plane transport properties of Si/Si1-xGexstructure and its FET performance by computer simulation

Transport properties of ungated Si/Si_1-xGe_x are studied by an ensemble Monte Carlo technique. The device performance is studied with a quantum hydrodynamic equation method using the Monte Carlo results. The phonon-scattering limited mobility is enhanced over bulk Si, and is found to reach 23000 cm²/Vs at 77 K and 4000 cm²/Vs at 300 K. The saturation velocity is increased slightly compared with the bulk value at both temperatures. A significant velocity overshoot, several times larger than the saturation velocity, is also found. In a typical modulation-doped field-effect-transistor, the calculated transconductance for a 0.18 μm gate device is found to be 300 mS/mm at 300 K. Velocity overshoot in the strained Si channel is observed, and is an important contribution to the transconductance. The inclusion of the quantum correction increases the total current by as much as 15%     

Flicker-Noise Improvement in 100-nm $L_{g} hbox{Si}_{0.50}hbox{Ge}_{0.50}$ Strained Quantum-Well Transistors Using Ultrathin Si Cap Layer

This letter presents a record low flicker-noise spectral density in biaxial compressively strained p-channel 100-nm L_gSi_0.50Ge_0.50 quantum-well FETs (QWFETs) with ultrathin Si (~2 nm) barrier layer and 1-nm EOT hafnium silicate gate dielectric. The normalized power spectral density of I_d fluctuations (S_Id/I_d ²) in Si_0.50Ge_0.50 QWFETs exhibits significant improvement by ten times over surface channel unstrained Si pMOSFETs at high V_g due to strong confinement of holes within the high-mobility QW and strong quantization in the ultrathin Si barrier layer enabled by low-thermal-budget device processing. The noise behavior in strained QW devices is found to evolve from being correlated mobility fluctuation dominated across most of V_g range to being Hooge mobility fluctuation dominated at very high V_g.     

Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes

Strained silicon-germanium (Si_0.6Ge_0.4) gated diodes have been fabricated and analyzed. The devices exhibit significantly enhanced gate-controlled tunneling current over that of coprocessed silicon control devices. The current characteristics are insensitive to measurement temperature in the 80 K to 300 K range. Independently extracted valence band offset at the strained Si_0.6Ge_0.4/Si interface is 0.4 eV, yielding a Si_0.6Ge_0.4 bandgap of 0.7 eV, which is much reduced compared to that of Si. The results are consistent with device operation based on quantum-mechanical band-to-band (BTB) tunneling rather than on thermal generation. Moreover, simulation of the strained Si_0.6Ge_0.4 device using a quantum-mechanical BTB tunneling model is in good agreement with the measurements.     

DC and RF performance of 0.25 μm p-type SiGe MODFET

The DC and RF performance of a 0.25 μm gate-length p-type SiGe modulation-doped field-effect transistor (MODFET) is reported. The hole channel consists of compressively strained Si_0.3Ge_0.7 layer grown on a relaxed Si_0.7Ge_0.3 buffer on a Si substrate. The combination of high-hole mobility, low-gate leakage current, and improved ohmic contact metallization results in an enhancement of the DC and RF performance. A maximum extrinsic transconductance (g(m_ext)) of 230 mS/mm was measured. A unity current gain cut-off frequency (fT) of 24 GHz and a maximum frequency of oscillation (f_max) of 37 GHz were obtained for these devices     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Strained‐SiGe Complementary MOSFETs Adopting Different Thicknesses of Silicon Cap Layers for Low Power and High Performance Applications

We introduce a strained‐SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si‐cap layers in n‐channel and p‐channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high‐electron‐mobility Si surface channel in nMOSFETs and a compressively strained high‐hole‐mobility Si_0.8Ge_0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate‐leakage levels. Unlike the conventional strained‐Si CMOS employing a relatively thick (typically > 2 µm) Si_xGe_1‐x relaxed buffer layer, the strained‐SiGe CMOS with a very thin (20 nm) Si_0.8Ge_0.2 layer in this study showed a negligible self‐heating problem. Consequently, the proposed strained‐SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.     

Fabrication of strained Si channel PMOSFET on thin relaxed Si1−xGex virtual substrate

A novel MBE-grown method using low-temperature Si technology is introduced into the fabrication of strained Si channel PMOSFETs. The thickness of relaxed Si_1−xGe_x epitaxy layer on bulk silicon is reduced to approximate 400 nm (x=0.2). The Ge fraction and relaxation of Si_1−xGe_x film are confirmed by DCXRD (double crystal X-ray diffraction) and the DC characteristics of strined Si channel PMOSFET measured by HP 4155B indicate that hole mobility μ_p has an maximum enhancement of 25% compared to similarly processed bulk Si PMOSFET.     

Device parameter optimization of strained Si channel SiGe/Sin-MODFET's using a one-dimensional charge control model

We have simulated the strained Si channel SiGe n-MODFET structure using a one-dimensional (1-D) self-consistent Schroedinger-Poisson charge control model. The quantum confinement effect has been investigated and key transistor parameters have been optimized for maximum f_T. It has been found that the doping concentration into the donor layer and the Ge mole fraction of the SiGe layers should be as high as possible, provided that the doping diffusion and the avalanche breakdown are under control and the crystalline quality of the epilayers is not significantly degraded. The optimum channel thickness was found to be between 5 and 7.5 nm. In addition, it has been shown that the thickness of the donor layer should be used for threshold voltage adjustment rather than for f_T improvement     

Growth and optical investigation of quaternary GaInAsSb/AlGaAsSb quantum wells

Infrared photoluminescence and high sensitive absorption measurements were performed on a quaternary GaInAsSb/AlGaAsSb strained multiple quantum well (MQW), as well as single quantum well (SQW) structures grown by molecular-beam epitaxy, to investigate its band offsets and subband behavior. Strong luminescence and well-resolved excitonic absorption peaks are observed even at room temperature, which is indicative of the good quality of our quaternary sample. By fitting the experimental results to the theoretical calculations, we find that the light holes are confined in well regions for Ga_0.75In_0.25As_0.04Sb_0.96/Al_0.22Ga_0.78As_0.02Sb_0.98 QWs (type I MQW) with a conduction-band offset ratio of Q_c = 0.66 ± 0.01. The transition from type I to type II for light holes is predicted theoretically and demonstrated directly by photoluminescence spectra in the SQW structures.     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

MBE growth and device applications of lattice-matched and strained heterostructures on (n11)-oriented and patterned substrates

The epitaxy of lattice-matched and strained semi-conducting films on patterned and misoriented substrates has led to new growth phenomena, material properties and device applications. Our work on InP- and GaAs-based heterostructures on (111)- and (311)-oriented substrates and strained heterostructures on planar and patterned (small area) substrates is described in this paper. The possibility of reliable and reproducible p-type doping of (311)A GaAs by Si during molecular-beam epitaxial growth and the application of such doping in the realization of high-performance electronic devices have been investigated. It is seen that p-type doping up to a free hole concentration of 4 × 10¹⁹ cm⁻³ is obtained at low ( 500°C) growth temperature and high As₄ flux. The incorporation of Si atoms into electrically active As sites is at least 95%. n-p-n heterojunction bipolar transistors grown by all-Si doping exhibit excellent current voltage characteristics and a common emitter current gain β = 240. Doped channel p-type heterojunction field-effect transistors have transconductance g_m = 25 mS/mm. We have experimentally and theoretically studied piezo-electric field effects in InP-based In_xGa_{1 − x}As/In_0.52Al_0.48As pseudomorphic quantum wells grown by molecular-beam epitaxy on (111)B InP substrates. The electro-optic coefficients of this material were measured and found to be much larger than that of GaAs. We have also investigated the consequences of altered growth modes on the epitaxy of highly strained InGaAs on patterned small area (001) GaAs substrates. Al_0.15Ga_0.85As/In_0.25Ga_0.75As pseudomorphic modulation-doped field-effect transistors and strained In_xGa_{1 − x}As/GaAs p-i-n photodiodes have been fabricated on patterned (100)-GaAs substrates and characterized. Compared with devices made on planar substrates, small area growth improves the dc transconductance by 40% and current gain cutoff frequency by 50% in the transistors. Photodiodes grown in small recesses (30 μm) exhibit 2–4 times higher quantum efficiency than those on planar substrates.     

Silicide/strained Si1-xGex Schottky-barrierinfrared detectors

By employing a thin silicon sacrificial cap layer for silicide formation, the authors successfully demonstrated Pd₂Si/strained Si_1-xGe_x Schottky-barrier infrared detectors with extended cutoff wavelengths. The sacrificial silicon eliminates the segregation effects and Fermi level pinning which occur if the metal reacts directly with Si_1-x Ge_x alloy. The Schottky barrier height of the silicide/strained Si_1-xGe_x detector decreases with increasing Ge fraction, allowing for tuning of the detector's cutoff wavelength. The cutoff wavelength was extended beyond 8 μm in PtSi/Si _0.85Ge_0.15 detectors. It is shown that high quantum efficiency and near-ideal dark current can be obtained from these detectors     

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V_T and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, σV_T , of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that σV_T, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V_T-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V_T-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 μm and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.