Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.     

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V_SS, negative-to-V_SS, positive-to-V_DD, and negative-to-V_DD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.     

一种CCD静电保护电路的设计

介绍了一种适用于电荷耦合器件(CCD)的静电保护电路.在对该静电保护电路工作原理分析的基础上,通过电路仿真确定了静电保护电路中MOS管的电学参数,再由半导体器件仿真确定了其工艺条件,并按此条件制作了静电保护电路.通过人体模型静电放电试验对该静电保护电路进行测试,结果表明CCD的抗静电能力由原来的不足100 V提高到450 V.     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.     

On-chip ESD protection design by using polysilicon diodes in CMOSprocess

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

System ESD robustness by co-design of on-chip and on-board protection measures

System-level ESD robustness is a crucial feature for any electronic system. However, a consistent design methodology including IC-level protection, on-board protection and physical design of the module is still missing. The idea of a simple correlation between IC-level and system-level ESD robustness levels is misleading. A thorough characterization of the high current behaviour of IO circuit and on-board protection elements provides the necessary data for a simulation based co-design of on-chip and on-board protection measures. The constraints for characterization and modelling are discussed and the various protection measures for improved system-level ESD robustness are presented. Applying this methodology allows the development of a cost optimized system-level ESD protection throughout the stages of a system design.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.     

Unique ESD failure mechanisms during negative to Vcc HBM tests

HBM ESD tests on two types of 0.6 μm DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground. These failures occurred at lower than expected ESD stress voltages due to power-up circuit interactions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin’s ESD protection circuit. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vcc bond pad can result in low voltage ESD failures.     

Do ESD fails in systems correlate with IC ESD robustness?

Integrated circuits (ICs) are qualified for their electrostatic discharge (ESD) robustness according to the well-known IC ESD standards Human Body Model, Machine Model, and Charged Device Model in order to guarantee safe handling in ESD protected areas. For electronic systems like mobile phones which are in direct use by consumers, certain robustness against system level ESD is demanded, too. As the ESD test methods of device and system level stress are completely different (waveforms, stress application, operating condition of the DUT, etc.), correlations between models of both worlds are difficult to establish. Therefore, the system vendors more and more demand a specified ESD robustness for devices (ICs) according to an ESD system level standard. Testing ICs to a system level ESD standard requires careful considerations; first ideas are summarized in the new Standard Practice “Human Metal Model” of the ESDA/ANSI. However, the approach of deriving system ESD robustness from IC robustness is currently too much simplified and bears severe potential risks. Nevertheless, there are methodologies and approaches to use IC ESD characterization for defining ESD protection concepts for systems. Appropriate high-current characterization of ICs can be the cornerstone for a successfully optimized system ESD protection.     

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.     

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.     

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.      

ESD degradation and robustness of RGB LEDs and modules: An investigation based on combined electrical and optical measurements

This paper presents an extensive analysis of the robustness of state-of-the-art RGB LEDs and LED modules submitted to Electrostatic Discharges (ESD). We studied both single RGB LEDs, and small modules constituted by the series connection of 2, 3, and 4 monochromatic LEDs. ESD events were simulated by a Transmission Line Pulser (TLP), capable of generating voltage pulses with a duration of 100 ns and increasing amplitude: after each of the pulses the electrical and optical parameters of the devices were monitored, with the aim of describing the effects of ESD events on the performance of the devices. The results indicate that: (i) the ESD robustness strongly depends on the LED wavelength; InGaN-based LEDs (the green and the blue LEDs) have a lower robustness with respect to the AlInGaP devices (i.e., red LEDs); (ii) non-destructive ESD events can induce significant modifications in the performance of the devices even below the failure voltage/current level; (iii) the ESD robustness of LED modules strongly depends on the robustness of each LED of the chain, and on the variability of the devices. The results presented in this paper provide important information for the design of high robustness multi-LED systems.     

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

ESD issues in compound semiconductor high-frequency devices and circuits

The need of ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.     

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime.All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002].The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress.The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.     

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.