单电感多路输出DC-DC转换器的建模与设计

建立了单电感多路输出(SIMO) DC-DC转换器的数学模型,通过Matlab验证了SIMO模型的可行性.为解决SIMO控制电路复杂以及静态工作电流大的问题,提出在电流域设计SIMO控制器的方法.该方法将SIMO多路输出电压反馈信号转换为电流信号,与基准电流信号和电感电流信号一并输入多环路PWM控制器,PWM控制器在电流域完成需要的运算及环路频率补偿.仿真结果表明,该算法可行,电路设计方法简洁,在0.13 μm CMOS工艺下,三通道SIMO的面积为0.76 mm2,静态电流为110 μA,驱动能力为200 mA.     

应用于可携式产品液晶显示器之低靜态电流与晶片面积的源极驱动电路架构

在这篇论文中,我们提出一种适用于 QCIF 解析度、262千色的薄膜电晶体液晶显示器,具有低静态电流和晶片面积的源极驱动电路架构.此类驱动晶片可以实际被应用于行动电话或其他高阶可攜式电子产品上.传统A、B、C等三种形式的源极驱动电路,需使用大量的运算放大器来驱动面板中的画素,和较大阻值的电阻式数位类比转换电路来产生珈玛电压,以保有最低的静态消耗电流.而我们提出的第四种源极驱动电路架构,仅使用二个运算放大器和较低电阻的电阻式数位类比转换电路,而且并不会增加静态消耗电流.因此,这颗源极驱动晶片,不仅可省下晶片面积、增加产品竞爭力,更可以降低静态功率的消耗以延长电池的续航力.我们所提出的运算放大器和源极驱动电路之原型晶片,是利用 3.3 V、0.35 μm ACMOS的制程技术来实现的.运算放大器电路的核心尺寸大小为 100 μm×50 μm,源极驱动电路为 400 μm×650 μm.由我们所提出的第四种驱动电路架构,晶片面积约可减少 54.25%,而静态消耗电流仅需 2.6%.     

中小屏幕TFT-LCD源驱动器电路设计

针对中小屏幕TFT-LCD源驱动器电路,提出了一种新型的源驱动器结构,重点设计了一种电流可调、采用零点补偿的轨对轨结构的输出缓冲电路.该电路结构不但满足了系统功能和面积要求,而且能够很好地适应未来TFT-LCD芯片的发展趋势.Hspice 仿真表明,在10 kΩ电阻,20 pF电容串连负载模型下的增益为90.7 dB,相位裕度75°,静态电流消耗1.1 μA,电路面积400 μm2,满足了系统要求.     

用于时钟芯片的Pierce晶体振荡器设计

分析了Pierce晶体振荡器的起振条件以及传统结构的局限性.基于CSMC 0.5 μmCMOS工艺设计实现了一种应用于时钟芯片的32.768 kHz的Pierce晶体振荡器电路.采用自动增益控制(AGC)结构,提高了频率稳定性,降低了功耗;使用单位增益放大器稳定静态工作点,有效地减小了版图的面积.通过Spectre对电路进行仿真,结果显示,电源电压在1.5～5.5 V电路输出频率都有较好的精度,最大的频率误差为0.085%,阿伦方差为2×10-8/s,在3 V电源电压下,静态平均电流仅300 nA,版图面积为300 μm×150 μm,满足时钟芯片低功耗、高稳定性、较宽的电源适用范围和节约版图面积的要求.     

一种基于密勒倍增的高性能LDO的设计

基于零极点跟踪技术,提出一种新的LDO频率补偿架构.利用密勒电容倍增原理和零极点跟踪技术,在很小的补偿电容面积下使LDO获得全负载范围内的环路稳定.摆率增强电路的应用使系统具有优越的负载瞬态调整性能.基于0.5 μm标准CMOS工艺,对LDO进行仿真验证.结果表明,系统空载下,静态电流为32 μA,且能提供最大200 mA的负载电流;在输出电容为2.2 μF、负载电流以200 mA/10 ns突变时,最大下冲电压仅为10 mV,没有明显的上冲.     

一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

为改善无片外电容LDO(Capacitor-Less Low-DropOut regulator,CL-LDO)的电源抑制比(Power Supply Rejection,PSR),本文提出一种低静态电流PSR自适应优化方案.采用push-pull放大器,避免复杂的频率补偿电路与片外大电容,缩小了面积.为优化中频段PSR,在功率管栅极注入一个与频率相关的补偿电流.采用低静态电流的补偿电流动态调整方案,减小压差和负载电流变化对PSR优化效果的影响.该LDO基于0.11μm CMOS工艺,芯片面积为0.026 mm².测试结果表明,在0.1～80 mA负载电流下,静态电流最大值为55μA.在8 kHz到1 MHz频率范围内,在不同压差和负载电流下,PSR最大优化值为21～37 dB.     

一种采用电压检测器的无片外电容FVF-LDO

提出了一种基于翻转电压跟随器(FVF)的无片外电容低压差线性稳压器(LDO)。采用电压检测器来检测输出电压,大幅改善了瞬态响应,克服了常规LDO面积大、需要使用片内大电容的缺点,仅消耗了额外的静态电流。该LDO采用90 nm CMOS工艺进行设计与仿真,面积为0.009 6 mm²,输入电压为1.2 V,压差为200 mV。结果表明,在50 pF负载电容、3～100 mA负载电流、300 ns跃迁时间的条件下,产生的上冲电压为65 mV,瞬态恢复时间为1 μs,产生下冲电压为89 mV,瞬态恢复时间为1.4 μs,且将负载调整率性能改善到0.02 mV/mA。     

一种低静态电流瞬态增强的无电容型LDO设计

基于推挽式结构能提高运算放大器压摆率的特性,设计了一款静态电流低、内含推挽式AB类放大器的无电容型低压差线性稳压器(LDO)。通过优化,改善了LDO的瞬态响应性能,与传统的LDO相比,所提出的无电容型LDO的静态电流明显减小。采用SMIC 0.18 μm CMOS工艺模型,利用Cadence工具对电路进行仿真验证。仿真结果表明,当输入电压为1.4~4 V时,优化后LDO的输出电压为1.2 V,静态电流为5.2 μA,最大负载电流达到100 mA,线性调整率为0.016%,负载调整率为0.67%,下过冲为157 mV,上过冲为121 mV,建立时间为1.5 μs。优化后电路瞬态响应性能改善了约50%,版图面积约为0.017 mm²。     

一种低温度系数的全CMOS基准电流源

基于传统基准电流源结构,增加了一条负反馈支路,将片上电阻的温度系数、晶体管载流子的温度系数与晶体管阈值电压的温度系数相互抵消,实现了基准电流源的温度补偿。测试结果表明,该基准电流源在1.1 V的电源电压下能正常工作。在1.2 V工作电压下,该基准电流源的静态电流仅为26 μA,输出平均电流为10.36 μA;当工作温度从-40 ℃到85 ℃变化时,电流的温度系数仅为3.79 ×10-4/℃。该电路采用55 nm CMOS工艺,其芯片面积为4 488 μm²,满足低功耗低成本的要求。     

低静态电流低压降CMOS线性稳压器

设计了一种100 mA低静态电流、低压降CMOS线性稳压器.通过使用与一般线性稳压器相类似的频率补偿方法,这种低压差线性稳压器获得了低静态电流,很好的电源调整率和负载调整率,以及很高的PSRR值.在0.5 μm工艺下的仿真结果表明,其消耗的静态电流只有5 μA,电源调整率和负载调整率分别为0.02 mV/V和0.002 mV/mA;在100 Hz时,其PSRR值为-90 dB,负载电容只有100 pF,可以很容易地集成到电路中.     

A robust low quiescent current power receiver for inductive power transmission in bio implants

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.     

Single-inductor dual-output (SIDO) DC–DC converters for minimized cross regulation and high efficiency in soc supplying systems

A compact size and high efficiency single-inductor dual-output (SIDO) DC–DC converter is proposed. The proposed SIDO DC–DC converter not only provides dual output sources (one buck and one boost outputs) but also has minimized cross regulation without using any external compensation components. Generally speaking, it is important to minimize the number of components and footprint area in the design of SIDO converters. However, usually large external compensation resistors and capacitors are required to stabilize DC–DC converters. Importantly, our proposed hysteresis mode operation can effectively avoid the oscillation problems that may exist in many SIMO designs. Furthermore, the dynamic dc current level like that in the continuous conduction mode (CCM) operation can make the proposed SIDO DC–DC converter achieve high conversion efficiency at light loads owing to small conduction loss. Experimental results show a high efficiency from 85% at light loads to 94% at heavy loads.     

Control of power factor correcting boost converter withoutinstantaneous measurement of input current

This paper proposes a new control method for the constant-frequency control of power factor correcting boost power converter using a sinewave template modulated PWM signal which eliminates the need for instantaneous measurement of the line current for the switching control of the boost converter. The control strategy is based on the notion that the line current can be forced to trace a deterministic waveform such as a sinusoid by considering the implicit model of the sinewave in the boost converter controller structure. The modulating sinewave template is generated using the line voltage, the boost converter output voltage and the load current. The paper provides the analysis and the design of the controller and presents simulation and implementation results to demonstrate its effectiveness     

Posicast-based digital control of the buck converter

The analysis, design, and microcontroller-based implementation of a digital controller using a Posicast element are presented for the buck converter. Posicast is a feedforward compensator that eliminates overshoot in system response, but the traditional approach is sensitive to variations in natural frequency. The new method described here reduces the undesirable sensitivity by using Posicast within a feedback loop. Compared to classical proportional-integral-derivative (PID) control, the new control results in lower noise in the control signal because the controller has a lower gain at high frequency. Furthermore, the authors' experiments indicate that the new controller is less sensitive to the inherent time delay associated with a digital controller for a dc-dc converter. The authors present a straightforward method to design controller parameters from the small-signal averaged model of the converter dynamics. Experimental results for a PID-controlled converter and Posicast-type controller are also compared.     

Predictive Digital-Controlled Converter With Peak Current-Mode Control and Leading-Edge Modulation

The main theme of this paper is to present the digital controller design of a power converter with predictive peak current-mode (PCM) control and leading-edge modulation. The advantages of the control and modulation technique include the reduction of the sampling frequency of the A/D converter, no need of slope compensation, and the provision of a fast dynamic current response. The discrete-time model of the converter is presented as the fundamental to digital controller design and followed by the digital controller design. Moreover, the effect of predictive PCM control with leading edge modulation on limit cycle is analyzed. It is known that the limit cycle can be effectively suppressed as the converter has a predictive PCM control and leading edge modulation. Experimental results will be included to support fully the theoretical analysis.      

Adaptive output voltage tracking controller for uncertain DC/DC boost converter

This paper presents a cascade output voltage control strategy for an uncertain DC/DC boost converter adopting an adaptive current controller in its inner loop. Considering the non-linearity, load uncertainties and parameter uncertainties of the converter, the proposed controller is designed following the conventional cascade voltage controller design method. The proposed method makes the following three contributions. First, a coordinate transformation is introduced for the inner loop, enabling avoidance of the singularity problem caused by the estimates of uncertain parameters. Second, a slight modification to the adaptation law is performed to guarantee closed-loop stability in the presence of the time-varying component of the load current. Third, the outer-loop controller is devised such that its performance can be adjusted without any parameter information. The closed-loop performance is demonstrated through simulations and experiments using the DSP28335 with a 3 kW DC/DC boost converter.     

Dual-Mode Multiple-Band Digital Controller for High-Frequency DC–DC Converter

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm² of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.     

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

This paper presents a single-inductor multiple-output (SIMO) converter operating in pseudo-continuous conduction mode (PCCM) and/or discontinuous conduction mode (DCM). With the proposed freewheel switching control, this converter can handle large load currents with a much smaller current ripple, while retaining low cross regulation. It can also work in DCM for high efficiency at light loads. A prototype of a single-inductor dual-output (SIDO) boost converter was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. The two outputs are regulated at 2.5 and 3.0 V, respectively. At an oscillator frequency of 1 MHz, the efficiency reaches 89.4% at a total output power of 320 mW. Compared with prior designs, both current and voltage ripples are reduced. This design can be extended to have multiple outputs and for different types of dc-dc conversions, or be applied to single-output converters for fast transient response.     

用降压型单电感多输出DC-DC变换器输出高电压

本文发现并证明了降压型单电感多输出DC-DC变换器当电感工作于连续导通模式下能够产生高于电源电压的输出。这个发现将降低需要同时输出高压和低压的DC-DC变换器的结构复杂性。本文实现了一个降压型结构的单电感双输出的直流变换器,供电电压3.3V,输出为1V和4V。实验结果很好的证明了本文的结论。     

Digital Predictive Feed-Forward Controller for a DC–DC Converter in Plasma Display Panel

This paper describes a new digital control method to enhance the dynamic performance of a dc-dc converter used in plasma display panel (PDP). A simple digital PID compensator with duty ratio feed-forward control is proposed to minimize the output voltage variation while the load current is continuously changing. The duty ratio feed-forward is calculated using noise-free load current information which is predicted by the available video data of the PDP. No separate current sensing circuit is required. A small signal z-domain feed-forward model is derived for the performance analysis and controller design. The proposed control method is experimentally verified on an asymmetrical half bridge dc-dc converter which supplies power to a 42 in PDP.