Characterization of MIS structures and thin film transistors using RF-sputtered HfO2/HIZO layers

MIS structures using HfO₂ and HIZO layers, both deposited by room temperature RF magnetron sputtering are fabricated for TFTs application and characterized using capacitance-voltage. The relative dielectric constant obtained at 1 kHz was 11, the charge carrier concentration of the HIZO was in the range of (2–3) × 10¹⁸ cm^− 3 and the interface trap density at flat band was smaller than 2 × 10¹² cm^− 2. The critical electric field of the HfO₂ layer was higher than 5 × 10⁵ V/cm, with a current density in the operating voltage range below 4 × 10^− 8 A/cm². The hysteresis and bias stress behavior of RF-sputtered HfO₂/HIZO MIS structures is presented. Fabricated HfO₂/HIZO TFTs worked in the operation voltage range below 8 V.     

High performance electric-double-layer amorphous IGZO thin-film transistors gated with hydrated bovine serum albumin protein

Device performance of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) has been improved greatly by using bovine serum albumin (BSA) as the top gate dielectric. BSA is a natural protein with acidic and basic amino acid residues, which is easily hydrated in air ambient. A typical a-IGZO TFT with hydrated BSA as the top gate dielectric exhibits a field-effect mobility (μ_FE) value of 113.5 cm² V⁻¹ s⁻¹ in saturation regime and a threshold voltage (V_TH) value of 0.25 V in air ambient. The excellent device performance can be well explained by the formation of electric double layers (EDLs) near the interfaces of a-IGZO/hydrated BSA and hydrated BSA/gate electrode. The reliability issue of a-IGZO TFTs gated with hydrated BSA has been also investigated by using the life time test without encapsulation. The V_TH value increases and μ_FE,sat value reduces slightly for the a-IGZO TFT and remain stabilized over 60 days.     

Self-assembled monolayers mediated charge injection for high performance bottom-contact poly(3,3′′′-didodecylquaterthiophene) thin-film transistors

Device performance of bottom-contact poly(3,3′′′-didodecylquaterthiophene) (PQT-12) thin-film transistors (TFTs) was significantly improved via surface-modification of Au source–drain (S–D) electrodes with 1-decanethiol and 1H,1H,2H,2H-perfluorodecanethiol self-assembled monolayers (SAMs). By improving the PQT-12 morphology and modulating the Schottky barrier at electrode/PQT-12 contacts, the thiol SAMs chemisorbed onto Au surfaces can improve the charge carrier injection at electrode/PQT-12 contacts and result in dramatic enhancements in device mobilities. Device mobilities up to 0.09 and 0.19 cm² V⁻¹ s⁻¹ were obtained in high performance bottom-contact PQT-12 TFTs with 1-decanethiol and 1H,1H,2H,2H-perfluorodecanethiol SAMs surface-modified Au S–D electrodes, compared with 0.015 cm² V⁻¹ s⁻¹ in PQT-12 TFTs with bare Au electrodes. This work may provide a simple path to the fabrication of high performance, low-cost, and solution-processable bottom-contact OTFTs using fine lithography technology.     

Defect modification in ZnInSnO transistor with solution-processed Al2O3 dielectric by annealing

The properties of solution-processed Al₂O₃ thin films annealed at different temperatures were thoroughly studied through thermogravimetry–differential thermal analysis, UV–vis-NIR spectrophotometer measurements, scanning electron microscopy, X-ray diffraction, atomic force microscopy and a series of electrical measurements. The solution-processed ZnInSnO thin films transistors (TFTs) with the prepared Al₂O₃ dielectric were annealed at different temperatures. The TFTs annealed at 600 °C have displayed excellent electrical performance such as the field-effect mobility of 116.9 cm² V⁻¹ s⁻¹ and a subthreshold slope of 93.3 mV/dec. The performance of TFT device could be controlled by adjusting the annealing temperature. The results of two-dimensional device simulations demonstrate that the improvement of device performance are closely related with the reduction of interface defects between channel and dielectric and subgap density of stats (DOS) in the channel layer.     

Electrical and optical properties of Cu2ZnSnS4 grown by a thermal co-evaporation method and its diode application

Cu₂ZnSnS₄ (CZTS) is low cost and constitutes non-toxic materials abundant in the earth crust. Environment friendly solar cell absorber layers were fabricated by a thermal co-evaporation technique. Elemental composition of the film was stated by energy dispersive spectroscopy (EDS). Some optical and electrical properties such as absorption of light, absorption coefficient, optical band gap charge carrier density, sheet resistance and mobility were extracted. Optical band gap was found to be as 1.44 eV, besides, charge carrier density, resistivity and mobility were found as 2.14×10¹⁹ cm⁻³, 8.41×10⁻⁴ Ω cm and 3.45×10² cm² V⁻¹ s⁻¹, respectively. In this study Ag/CZTS/n-Si Schottky diode was fabricated and basic diode parameters including barrier height, ideality factor, and series resistance were concluded using current–voltage and capacitance–voltage measurements. Barrier height and ideality factor values were found from the measurements as 0.81 eV and 4.76, respectively, for Ag/CZTS/n-Si contact.     

In0.75Ga0.25As channel layers with record mobility exceeding 12,000 cm2/Vs for use in high-κ dielectric NMOSFETs

In_0.75Ga_0.25As channel layers with a record mobility exceeding 12,000 cm²/Vs for use in high-κ dielectric NMOSFETs have been fabricated. The device structures which have been grown by molecular beam epitaxy on 3″ semi-insulating InP substrate comprise a 10 nm strained In_0.75Ga_0.25As channel layer and a high-κ oxide based dielectric layer (κ ≅ 20). Electron mobilities of 12,033 and 7,042 cm²/Vs have been measured for sheet carrier concentrations n_s of 2.5 × 10¹² and 6 × 10¹² cm⁻², respectively.     

AlGaN/GaN Schottky barrier diodes on silicon substrates with various Fe doping concentrations in the buffer layers

This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 10¹⁷ cm^− 3 realized the highest on-resistance (R_ON) and turn-on voltage (V_ON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 10¹⁷ cm^− 3, which exhibited a R_ON of 31.6 mΩ-cm², a V_ON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer.     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.     

Sputtered oxides used for passivation layers of amorphous InGaZnO thin film transistors

Four sputtered oxide films (SiO₂, Al₂O₃, Y₂O₃ and TiO₂) along with their passivating amorphous InGaZnO thin film transistors (a-IGZO TFTs) were comparatively studied in this paper. The device passivated by an Al₂O₃ thin film showed both satisfactory performance (μ_FE=5.3 cm²/V s, I_on/I_off>10⁷) and stability, as was probably related to smooth surface of Al₂O₃ thin films. Although the performance of the a-IGZO TFTs with a TiO₂ passivation layer was also good enough (μ_FE=3.5 cm²/V s, I_on/I_off>10⁷), apparent V_th shift occurred in positive bias-stress tests due to the abnormal interface state between IGZO and TiO₂ thin films. Sputtered Y₂O₃ was proved no potential for passivation layers of a-IGZO TFTs in this study. Despite unsatisfactory performance of the corresponding a-IGZO TFT devices, sputtered SiO₂ passivation layer might still be preferred for its high deposition rate and excellent transparency which benefit the mass production of flat panel displays, especially active-matrix liquid crystal displays.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Electrochemical growth of tin(II) oxide films: Application in photocatalytic degradation of methylene blue

We have investigated the semiconducting and photoelectrochemical properties of SnO films grown potentiostatically on tin substrate. The oxide is characterized by X-ray diffraction, scanning electron microscopy and Raman spectroscopy. The anodic process corresponds to the formation of SnO·nH₂O pre-passive layer that is removed upon increasing potential due to surface etching at the metal/oxide interface. SnO films deposited for long durations (>50 mn) are uniform and well adhered; they thicken up to ~50 nm by diffusion-controlled process and the growth follows a direct logarithmic law. The thickness is determined by coulometry and the X-ray diffraction indicates the tetragonal SnO phase (SG: P4/mmm) with a crystallite size of 32 nm. The Mott–Schottky plot is characteristic of n type conductivity with an electrons density of 5.72×10¹⁸ cm⁻³, a flat band potential of −0.09 V_SCE and a depletion width of ~10 nm. The valence band, located at 5.91 eV below, vacuum is made up of hybridized O²⁻:2p Sn²⁺:5s while the conduction band (4.45 eV) derives from Sn²⁺:5p orbital. The electrochemical impedance spectroscopy (EIS) measured in the range (10⁻²–10⁵ Hz) shows the contribution of the bulk and grain boundaries. The energy band diagram predicts the photodegradation of methylene blue on SnO films. 67% of the initial concentration (10 mg L⁻¹) disappears after 3 h of exposure to visible light (9 mW cm⁻²) with a quantum yield of 0.072.     

Effect of gate insulator thickness on device performance of InGaZnO thin-film transistors

Top-contact thin-film transistors (TFTs) are fabricated in this work using atomic layer deposition (ALD) Al₂O₃ as the gate insulator and radio frequency sputtering InGaZnO (IGZO) as the channel layer so as to investigate the effect of Al₂O₃ thickness on the performance of IGZO-TFTs. The results show that TFT with 100-nm-thick Al₂O₃ (100 nm-Al₂O₃-TFT) exhibits the best electrical performance; specifically, field-effect mobility of 5 cm²/Vs, threshold voltage of 0.95 V, I_on/I_off ratio of 1.1×10⁷ and sub-threshold swing of 0.3 V/dec. The 100 nm-Al₂O₃-TFT also shows a substantially smaller threshold voltage shift of 1.1 V after a 10 V gate voltage is applied for 1 h, while the values for TFTs with an Al₂O₃ thickness of 220 and 280 nm are 1.84 and 2 V, respectively. The best performance of 100 nm-Al₂O₃-TFT can be attributed to the larger capacitance and the smaller amount of total trap centers possessed by a thinner insulator compared to the thicker ones.     

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼10⁶ and mobility ∼1 cm²/V s in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120 Hz to >2 kHz with rail voltages, V_DD, increasing from −15 V to −90 V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8 h of continuous operation at V_DD = −60 V, the frequency of a 7-stage RO remained almost constant at ∼1.4 kHz albeit that the output signal amplitude decreased from ∼22 V to ∼10 V. Over the next 30 days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.     

Effects of RTA temperatures on conductivity and micro-structures of boron-doped silicon nanocrystals in Si-rich oxide thin films

In this work, the B-doped Si rich oxide (SRO) thin films were deposited and then annealed using rapid thermal annealing (RTA) to form SiO₂-matrix silicon nanocrystals (Si NCs). The effects of the RTA temperatures on the structural properties, conduction mechanisms and electrical properties of B-doped SRO thin films (BSF) were investigated systematically using Hall measurements, Fourier transform infrared spectroscopy and Raman spectroscopy. Results showed that the crystalline fraction of annealed BSF increased from 41.3% to 62.8%, the conductivity was increased from 4.48×10⁻³ S/cm to 0.16 s/cm, the carrier concentration was increased from 8.74×10¹⁷ cm⁻³ to 4.9×10¹⁸ cm⁻³ and the carrier mobility was increased from 0.032 cm² V⁻¹ s⁻¹ to 0.2 cm² V⁻¹ s⁻¹ when the RTA temperatures increased from 1050 °C to 1150 °C. In addition, the fluctuation induced tunneling (FIT) theory was applicable to the conduction mechanisms of SiO₂-matrix boron-doped Si-NC thin films.     

Charge trapping in ultrathin Gd2O3 high-k dielectric

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10⁻²⁰ cm². The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 10¹² eV⁻¹ cm⁻² near the valence band edge.     

Electronic properties of Si/Si-Ge Alloy/Si(100) heterostructures formed by ECR Ar plasma CVD without substrate heating

By using our low-energy Ar plasma enhanced chemical vapor deposition (CVD) at a substrate temperature below 100 °C during plasma exposure without substrate heating, modulation of valence band structures and infrared photoluminescence can be observed by change of strain in a Si/strained Si_0.4Ge_0.6/Si(100) heterostructure. For the strained Si_0.5Ge_0.5 film, Hall mobility at room temperature was confirmed to be as high as 660 cm² V⁻¹ s⁻¹ with a carrier concentration of 1.3×10¹⁸ cm⁻³ for n-type carrier, although the carrier origin was unclear. Moreover, good rectifying characteristics were obtained for a p⁺Si/nSi_0.5Ge_0.5 heterojunction diode. This indicates that the strained Si-Ge alloy and Si films and their heterostructures epitaxially grown by our low-energy Ar plasma enhanced CVD without substrate heating can be applicable effectively for various semiconductor devices utilizing high carrier mobility, built-in potential by doping and band engineering.