基于薄埋氧层及三顶层硅的SOI高压LDMOS研究

详细研究了一种基于薄埋氧层及三层顶层硅衬底(Triple-Layer Top Silicon,TLTS)的SOI高压LDMOS器件。该结构在SOI介质层上界面的顶层硅内引入一高浓度n⁺层,当器件处于反向阻断状态时,高浓度n⁺区部分耗尽,漏端界面处已耗尽n⁺层内的高浓度电离施主正电荷可增强介质层电场,所产生的附加电场将调制漂移区内的电场,防止器件在漏端界面处被提前击穿,从而可在较薄的埋氧层(BOX)上获得较高耐压。在0.4 μm BOX上获得了624 V的耐压。与几种SOI器件相比,所提出的TLTS LDMOS器件具有较高优值(FOM)。     

A novel double RESURF LDMOS for HVIC's

The viability of a fully implanted double RESURF technology using a linearly varying doping of p-layer at the surface [Electron. Lett. 32 (12) (1996) 1092-1093] is demonstrated for the first time. Incorporating such a layer allows the drift region charge to be doubled without degradation of breakdown voltage. Experimental results of a high-voltage LDMOS in such a technology show a reduction in the on-resistance by one-half of that of a conventional RESURF based structure.     

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

We studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field-effect transistor (SOI-MOSFET) and compared the performance to that of a conventional SOI-MOSFET (C-SOI). Our structure, called a SIG-SOI MOSFET, includes main and side gates with an optimum voltage difference between them. The voltage difference leads to an inverted channel as an electrical drain extension under the side gate. This channel creates a stepped potential distribution along the channel that it cannot be seen in the C-SOI MOSFETs. The voltage difference controls the channel properly and two-dimensional two-carrier device simulations revealed lower threshold voltage variations, larger breakdown voltage, higher voltage gain, lower hot carrier effects, improved drain-induced barrier lowering, lower drain conductance, higher unilateral power gain, and lower leakage current compared to a C-SOI device. Thus, our proposed structure has higher performance than a typical C-SOI structure.     

一种新型高压Triple RESURF SOI LDMOS

提出了一种新型Triple RESURF SOI LDMOS结构,该结构有一个Ｐ型埋层。首先,耗尽层能够在Ｐ型埋层的上下同时扩展与Triple RESURF机理相同,使得漂移区浓度提高,导通电阻降低。其次,当漂移区浓度较高时,Ｐ型埋层起到了降低体内电场的作用,并能够提高漏端纵向电场使得其电场分布更加均匀从而耐压增加。Triple RESURF结构在SOI LDMOS中首次提出。在６微米厚的SOI层以及２微米厚的埋氧层中获得了耐压300V的Triple RESURF SOI LDMOS,其导通电阻从Double RESURF SOI LDMOS的17.2mΩ.cm2降低到13.8mΩ.cm2。当外延层厚度增加时, Triple RESURF结构的效果更加明显,在相同耐压下,相对于Double RESURF,该结构能够在400V和550V的SOI LDMOS中分别降低29%和38%的导通电阻。     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

一种用于高压防护的新型闩锁免疫LDMOS

横向双扩散MOSFET(LDMOS)由于其高击穿电压特性而被认为是适合在高压中应用的防止静电放电(ESD)现象的保护器件.在传统结构中,LDMOS的鲁棒性相对较差,这是器件自身固有的不均匀导通特性和Kirk效应导致的.可将可控硅整流器(SCR)嵌入到LDMOS结构(即NPN_LDMOS)中.然而,SCR固有的正反馈效应...     

High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

一种用于高压应用的700V BCD工艺平台

针对高压应用领域,建立了一种700V的高压 BCD兼容工艺平台。采用全注入技术在p型单晶衬底上,仅用10张光刻版即实现了700V nLDMOS、200V nLDMOS、80V nLDMOS、60V nLDMOS、40V nLDMOS、700V nJFET和低压器件的单片集成。工艺中没有采用外延层或埋层,极大地节约了制造成本。其中,高压双RESURF LDMOS的击穿电压为800V,比导通电阻为206.2 mohm.cm₂。该700V 高压 BCD兼容工艺平台具有低成本、工艺简单的优势,可使得功率集成电路产品具有较小的芯片面积。     

A novel NLDMOS with a high ballast resistance for ESD protection

To prevent the non-uniform conduction phenomenon caused by the Kirk effect in an NLDMOS under ESD stress, a novel NLDMOS structure is proposed. High electron injection current is the base of Kirk effect. Higher electron injection can makes the Kirk effect more serious and lead easily to the non-uniform conduction phenomenon. By splitting the drain N＋ with the field oxide in the proposed structure, the crowded current can lead to a higher voltage drop on the ballast resistance. Therefore, the non-uniform conduction is suppressed, and its failure current is much improved.     

A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

一种SOI nLDMOS的开态特性设计

介绍了一种用于高压电平位移电路的SOInLDMOS器件结构,对其漂移区、sink区、bufferN场板等结构参数进行器件工艺联合仿真,并分析相关结构参数对开态特性的影响,用于指导高压MOS器件尤其是基于SOI的横向MOS器件的开态特性设计。采用优化的参数,器件关态击穿电压为296V,开态击穿电压为265V,比导通电阻为60．9mΩ·cm^2。     

一种新的二维光正交码的构造与性能分析

以OCFHC(一次重合跳频码)作为时间扩频序列,OCS(单重合序列)作为波长跳频序列,构造了一种新的二维光正交码OCFHC/OCS。分析OCFHC/OCS的码字性能,得到了码字的互相关均值表达式,并对该码字的误码率进行了仿真比较。仿真结果表明,当码重和任意两个相邻"切普"波长的最小间隔一定时,增加OCFHC/OCS码的跳波长数,不仅可以降低MWOCDMA(多波长光码分多址)系统的误码率,还可以增加码字容量;与OOC(光正交码)/OCS码相比,OCFHC/OCS码的码字性能更优。     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

Silicon-on-Ferroelectric Insulator field effect transistor (SOFFET): Partially depleted structure for sub-60 mV/decade applications

This paper presents the concept of a new field effect transistor (FET) named a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). Our design proposes to utilize the negative capacitance (NC) of ferroelectric material in a partially depleted silicon-on-insulator (PD-SOI) device structure. We suggest to substitute the buried insulator oxide (SiO₂) inside the SOI substrate with a ferroelectric material, which converts it to the Silicon-on-Ferroelectric Insulator (SOF) substrate. The proposed integration of a ferroelectric material into the body of the MOSFET device will provide the required NC effect to overcome the fundamental thermionic barrier of the current and emerging FETs. This new SOFFET device would provide enhanced device gain, speed and channel conduction. A theoretical model is developed to validate the concept of the new device, which can lower the subthreshold swing (S) below the theoretical minimum S=60 mV/decade that is imposed by the thermodynamic limit (kT/q) of the FET devices. Analytical models have been derived to show that the subthreshold swing and the threshold voltage of the proposed device depend on the thicknesses of ferroelectric insulator and gate oxide, and the doping profile of the silicon body. It has been demonstrated that by carefully optimizing different geometric and electrical parameters the proposed PD-SOFFET can provide S value significantly below 60 mV/decade.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

In order to minimize leakage current increase under total ionizing dose （TID） radiation in high density memory circuits, a new isolation technique, combining deep trench isolation （DTI） between the wells, local oxi- dation of silicon （LOCOS） isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator （PD-SOI） technology. This ra- diation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single tran- sistors under 1 Mrad（Si） radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad（Si）, with only 50% increase of the active power consumption in read mode.