Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Role of Schottky barrier height at source/drain contact for electrical improvement in high carrier concentration amorphous InGaZnO thin film transistors

We report the fabrication of bottom-gate thin film transistors (TFTs) at various carrier concentrations of an amorphous InGaZnO (a-IGZO) active layer from ~10¹⁶ to ~10¹⁹ cm⁻³, which exceeds the limit of the concentration range for a conventional active layer in a TFT. Using the Schottky TFTs configuration yielded high TFT performance with saturation mobility (μ_sat), threshold voltage (V_TH), and on off current ratio (I_ON/I_OFF) of 16.1 cm²/V s, −1.22 V, and 1.3×10⁸, respectively, at the highest carrier concentration active layer of 10¹⁹ cm⁻³. Other carrier concentrations (<10¹⁹ cm⁻³) of IGZO resulted in a decrease of its work function and increase in activation energy, which changes the source/drain (S/D) contact with the active layer behavior from Schottky to quasi Ohmic, resulting in achieving conventional TFT. Hence, we successfully manipulate the barrier height between the active layer and the S/D contact by changing the carrier concentration of the active layer. Since the performance of this Schottky type TFT yielded favorable results, it is feasible to explore other high carrier concentration ternary and quaternary materials as active layers.     

High-speed organic single-crystal transistors gated with short-channel air gaps: Efficient hole and electron injection in organic semiconductor crystals

Short-channel, high-mobility organic filed-effect transistors (OFETs) are developed based on single crystals gated with short-channel air gaps. The high hole mobility of 10 cm²/Vs for rubrene, and high electron mobility of 4 cm²/Vs for PDIF-CN₂ crystals are demonstrated even with a short channel length of 6 μm. Such performance is due to low contact resistance in these devices estimated to be as low as ～0.5 kΩ cm at gate voltage of ?4 V for rubrene. With the benefit of the short channel length of 4.5 μm in a new device architecture with less parasitic capacitance, the cutoff frequency of the rubrene air–gap device was estimated to be as high as 25 MHz for drain voltage of ?15 V, which is the fastest reported for p-type OFETs, operating in ambient conditions.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5 × 10¹⁷ cm⁻³ and a minimum length of 20 nm enables 5 nm TFETs to exhibit favorable on–off switching characteristics. In sub-20 nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25 nm to sustain reversely biased drain voltage of 0.7 V. The asymmetric Si_1−xGe_x source heterojunction is combined with the minimum drain design in 5 nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TFETs.     

Channel width effect for organic thin film transistors using TIPS-pentacene employed as a dopant of poly-triarylamine

The effects of the physical channel width on the characteristics of organic thin film transistors (OTFTs), made with 6,13-bis(triisopropyl-silylethynyl)-pentacene (TIPS-pentacene) embedded into poly-triarylamine (PTAA, hole conductor within an active channel), have been examined in this paper. The devices are estimated by measuring the drain-source current (I_DS) for different contact metals such as Au and Ag, at fixed gate and drain voltages. The results show that the threshold voltage (V_T) and I_DS increase with increasing channel width. Furthermore, it has been observed that the field effect mobility is dependent on V_T, which is influenced by the channel width. The OTFTs, produced using Au and Ag contacts, exhibited the highest values of mobility in the saturation regime, namely 5.44 × 10^?2 and 1.33 × 10^?2 cm²/Vs, respectively.     

A fundamental understanding of nickel oxide based resistive random access memory with high percentage of oxygen

In this paper, we report the fundamental properties of NiO_x based Resistive RAM (RRAM) devices with Al top electrode and Ni bottom electrode. The NiO_x deposition was performed in a relatively high oxygen environment. The initial J–V curves in positive and negative bias indicated symmetric behavior in spite of a significant difference in the vacuum work functions of Al and Ni. The capacitance–voltage characterizations indicated NiO_x to be a p-type semiconductor with acceptor doping density between 6 × 10¹⁸ cm^?3 and 5 × 10²⁰ cm^?3. Switching behavior was observed after electroforming the devices. The devices failed after multiple switching cycles by switching into a relatively low conductive state. The mechanism of failure was attributed to the formation of Al₂O₃ due to a slow oxidation of Al electrodes with repeated cycles.     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.     

Iridium-based semi-transparent current spreading layer on short-period-superlattice (SPS) tunneling contact of InGaN/GaN LEDs

Iridium-containing and Ni(4 nm)/Au(6 nm) films were evaporated separately on the n⁺-InGaN–GaN short-period-superlattice (SPS) structure of light-emitting diodes (LEDs). The collective deposition of iridium and other metals as an ohmic contact induces the formation of highly transparent IrO₂, which helps to enhance the light output and decrease the series resistance of LEDs. By comparing different metal films used as current spreading contact layer, Ir/Ni film annealed at 500 °C for 20 min in O₂ ambient renders devices with lowest turn-on voltage at 20 mA and highest luminous intensity. Moreover, we also analyzed films using atomic force microscopy (AFM) with an emphasis on studying how the surface quality of Ir/Ni and Ni/Au films influences the current spreading and luminosity of LEDs.     

Electrical properties of Π-conjugated Fe-TPP molecular solar cell device

A heterojunction device of Au/Fe-TPP/n-Si/Al was assembled by thermally evaporated deposition. The dark current density–voltage characteristics of device were investigated. Results showed a rectification behavior. Measurements of thermo electric power confirm that Fe-TPP thin film behaves as p-type semiconductors. Electronic parameters such as barrier height, diode ideality factor, series resistance, shunt resistance were found to be 0.83 eV, 1.5, 7 × 10⁵ Ω and 2 × 10¹⁰ Ω, respectively. The Au/Fe-TPP/n-Si/Al device indicates a photovoltaic behavior with an open circuit voltage V_oc of 0.52 V, short circuit current I_sc of 2.22 × 10^?6 A, fill factor FF of 0.49 and conversion efficiency 1.13% under white light illumination power 50 W/m².     

To observe bidirectional negative differential resistance at room temperature by narrowing transport channels for charge carriers in vertical organic light-emitting transistor

Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ～10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq₃)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (～10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Ultra-thin and graded sliver electrodes for use in transparent pentacene field-effect transistors

The authors report the fabrication of efficient and transparent pentacene field-effect transistors (FETs) using a graded structure of ultra-thin silver (Ag) source and drain (S–D) electrodes. The S–D electrodes were prepared by thermal evaporation with a controlled deposition rate to form Ag layer with a graded structure, leading to a reduced injection barrier and smoothing the contact surface between the electrode and the pentacene channel. The sheet resistance of such Ag electrode was found to be as low as 9 Ω/sq. In addition, a hole-only behavior of device with Ag electrode characterized by current–voltage measurement and conductive atomic-force microscopy shows the injection property of high current flowing as compared with device using Au electrode, resulting in an efficient injection condition existing at the interface of the graded Ag/pentacene. Device characterization indicates the transparent pentacene FET with a graded ultra-thin Ag electrode and organic capping layer of N,N′-di(1-naphthyl)-N,N′-diphenylbenzidine exhibits a high transmission rate of ∼75% in the range of visible light from 400 to 550 nm, a threshold voltage of −6.0 V, an on–off drain current ratio of 8.4 × 10⁵, and a field-effect mobility of 1.71 cm²/V s, thus significantly outperforming pentacene FETs with multilayer oxide electrodes or other transparent thin metal layers.     

Electrical and photoelectrical characterization of an organic–inorganic heterojunction based on quinoline yellow dye

An organic–inorganic contact was fabricated by forming a thin film of quinoline yellow dye (QY) on a p-Si wafer and evaporating Al metal on the film. The current–voltage (I–V) and capacitance–voltage (C–V) measurements of Al/QY/p-Si heterostructure were applied in dark and room temperature to calculate the characteristic parameters of diode like ideality factor, barrier height and series resistance. Ideality factor and barrier height values were found as 1.23 and 0.87 eV from I–V data, respectively. The series resistance value of the device was determined as 1.8 kΩ by using modified Norde function. The C–V measurements were carried out at different frequencies and it was seen that capacitance value decreased with increasing frequency. Interface state density distribution was calculated by means of I–V measurement. In addition the optical absorption of thin QY film on glass was measured and optical band gap of the film was found as 2.73 eV. Furthermore, I–V measurements of Al/QY/p-Si/Al were taken under illumination between 40 and 100 mW/cm². It was observed that reverse bias current of the device increased with light intensity. Thus, the heterojunction had a strong response to the light and it can be suitable for electrical and optoelectronic applications like a photodiode.     

Determination of contact parameters of Ni/n-GaP Schottky contacts

The electrical analysis of Ni/n-GaP structure has been investigated by means of current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) measurements in the temperature range of 120–320 K in dark conditions. The forward bias I–V characteristics have been analyzed on the basis of standard thermionic emission (TE) theory and the characteristic parameters of the Schottky contacts (SCs) such as Schottky barrier height (SBH), ideality factor (n) and series resistance (R_s) have been determined from the I–V measurements. The experimental values of SBH and n for the device ranged from 1.01 eV and 1.27 (at 320 K) to 0.38 eV and 5.93 (at 120 K) for Ni/n-GaP diode, respectively. The interface states in the semiconductor bandgap and their relaxation time have been determined from the C–f characteristics. The interface state density N_ss has ranged from 2.08 × 10¹⁵ (eV^?1 m^?2) at 120 K to 2.7 × 10¹⁵ (eV^?1 m^?2) at 320 K. C_ss has increased with increasing temperature. The relaxation time has ranged from 4.7 × 10^?7 s at 120 K to 5.15 × 10^?7 s at 320 K.     

Electrical characterization of inorganic-on-organic diode based InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS)

The electronic properties of metal–organic semiconductor-inorganic semiconductor diode between InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS) polymeric organic semiconductor film have been investigated via current–voltage and capacitance–voltage methods. The Al/PEDOT:PSS/p-InP contact exhibits a rectification behavior with the barrier height value of 0.98 eV and with the ideality factor value of 2.6 obtained from their forward bias current voltage (I–V) characteristics at the room temperature greater than the conventional Al/p-InP (0.83 eV, n = 1.13). This increase in barrier height and ideality factor can be attributed to PEDOT:PSS film formed at Al/p-InP interface.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

Formation of low-resistance and transparent indium tin oxide ohmic contact for high-brightness GaN-based light-emitting diodes using a Sn–Ag interlayer

We report on the formation of low-resistance and highly transparent indium tin oxide (ITO) ohmic contacts to p-GaN using a Sn–Ag alloy interlayer. Although the as-deposited Sn–Ag(6 nm)/ITO(200 nm) contacts show non-ohmic behaviors, the scheme becomes ohmic with specific contact resistance of 4.72×10⁻⁴ Ω cm² and produce transmittance of ∼91% at wavelength of 460 nm when annealed at 530 °C. Blue light-emitting diodes (LEDs) fabricated with the Sn–Ag/ITO contacts give forward-bias voltage of 3.31 V at injection current of 20 mA. LEDs with the Sn–Ag/ITO contacts show the improvement of the output power by 62% (at 20 mA) compared with LEDs with Ni/Au contacts.     

Ferroelectric random access memory based on one-transistor–one-capacitor structure for flexible electronics

We have demonstrated a low temperature process for a ferroelectric non-volatile random access memory cell based on a one-transistor–one-capacitor (1T1C) structure for application in flexible electronics. The n-channel thin film transistors (TFTs) and ferroelectric capacitors (FeCaps) are fabricated using cadmium sulfide (CdS) as the semiconductor and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer as the ferroelectric material, respectively. The maximum processing temperature for the TFTs is 100 °C and 120 °C for the FeCaps. The TFT shows excellent access control of the FeCap in the 1T1C memory cell, and the stored polarization signals are undisturbed when the TFT is off. The fabricated 1T1C memory cell was also evaluated in a FRAM circuit. The memory window on the bit line was demonstrated as 2.3 V, based on the 1T1C memory cell with a TFT having dimensions of 80 μm/5 μm (W/L) and a FeCap with an area of 0.2 × 10^?3 cm² using a bit line capacitor of 1 nF pre-charged at 17.2 V. The 1T1C memory cell is fabricated using photolithographic processes, allowing the integration with other circuit components for flexible electronics systems.