Specification and Standardization of a Java Trusted Computing API

The paradigm of Trusted Computing promises a new approach to improve the security of computer systems. The core functionality, based on a hardware component known as Trusted Platform Module, is integrated into commodity hardware. However, operating system integration and application software support remains limited at present. In particular, for Java, the most widely used platform‐independent computing environment, there is currently no generally accepted Trusted Computing API. In this article, we describe the design of a high‐level API for Trusted Computing. We report on the current state of the Trusted Computing Group's software architecture and on previous approaches targeting Java. We derive our requirements and design goals and describe a novel API design. We report on our transparent approach to standardization in the Java Community Process. The result of this effort is the API we propose in the Java Specification Request 321. In this work, we not only present the design of this new API but also discuss implementation and testing strategies. Copyright © 2011 John Wiley & Sons, Ltd.     

Supporting dynamic interactions among Web-based information sources

The ubiquity of the World Wide Web offers an ideal opportunity for the deployment of highly distributed applications. Now that connectivity is no longer an issue, attention has turned to providing a middleware infrastructure that will sustain data sharing among Web-accessible databases. We present a dynamic architecture and system for describing, locating, and accessing data from Web-accessible databases. We propose the use of flexible organizational constructs service links and coalitions to facilitate data organization, discovery, and sharing among Internet-accessible databases. A language is also proposed to support the definition and manipulation of these constructs. The implementation combines Java, CORBA, database API (JDBC), agent, and database technologies to support a scalable and portable architecture interconnecting large networks of heterogeneous and autonomous databases. We report on an experiment to provide uniform access to a Web of healthcare-related databases     

MagicMeeting: A Collaborative Tangible Augmented Reality System

We describe an augmented reality (AR) system that allows multiple participants to interact with 2D and 3D data using tangible user interfaces. The system features face-to-face communication, collaborative viewing and manipulation of 3D models, and seamless access to 2D desktop applications within the shared 3D space. All virtual content, including 3D models and 2D desktop windows, is attached to tracked physical objects in order to leverage the efficiencies of natural two-handed manipulation. The presence of 2D desktop space within 3D facilitates data exchange between the two realms, enables control of 3D information by 2D applications, and generally increases productivity by providing access to familiar tools. We present a general concept for a collaborative tangible AR system, including a comprehensive set of interaction techniques, a distributed hardware setup, and a component-based software architecture that can be flexibly configured using XML. We show the validity of our concept with an implementation of an application scenario from the automotive industry.     

A reconfigurable bus structure for multiprocessors with bandwidth reuse

Shared bus is one of the most popular communication media for tightly coupled multiprocessing environments. However, a shared bus can provide only limited bandwidth, a fact that limits its usability. In this paper we propose a re-configurable bus structure with both temporal and spatial/spectral bandwidth expansion and describe a method for reusing part of the bandwidth available from temporal and spatial/spectral bandwidth expansion without introducing any buffering delay. Two polynomial time algorithms are developed to optimally reconfigure the bus under the design constraints for a given traffic pattern. For one algorithm the architecture is geared to obtain low average system response time. The other algorithm minimizes the system response time on a different architecture that is designed to reduce the disparity of response time among different nodes. We have compared the performance of reconfigured buses with that of the traditional slotted buses for uniform and localized traffic patterns and found that the reconfigured bus outperforms the traditional slotted bus substantially in most practical scenarios.     

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.     

基于PXI总线的MIC总线通讯模块设计

MIC总线是专门为了解决现代军事及工业领域中极其复杂和恶劣的工作环境下电力/数据的分配和管理而开发的一种具有结构简单及高可靠性的现场总线;在详细分析MIC总线的体系结构和通信协议之后,提出了基于PXI总线体系结构的MIC总线通讯模块的软硬件设计方案;系统可通过PXI总线灵活配置MIC的各种通讯模式参数,具有即插即用、高可靠性和小型化易集成等特点;实验证明,主模块PIM工作模式与远程从模块间数据通讯稳定且可靠,对国内MIC总线的研究与应用有重要意义。     

Message-based priority access to local networks

Hyperchannel interfaces are designed to interface computer mainframes and peripheral equipment to a high speed bus to form a local network. Each interface executes a distributed control contention access algorithm operation revolves about fixed priorities assigned to the individual interfaces. The access algorithm is extended to provide for message-assigned priorities, to provide better bus access rights for higher classes of messages at the expense of degraded access rights for the lower classes of messages. The extension requires little additional new hardware but instead employs a replication in each interface of existing hardware.The original hyperchannel interface access mechanism is explained. The algorithm extension is described and two models are developed to assess its effect on message transmission access rights, and via these models the viability of the extended algorithm can be demonstrated quantitatively.     

NUMA-aware image compositing on multi-GPU platform

Sort-last parallel rendering is widely used. Recent GPU developments mean that a PC equipped with multiple GPUs is a viable alternative to a high-cost supercomputer: the Fermi architecture of a single GPU supports uniform virtual addressing, providing a foundation for non-uniform memory access (NUMA) on multi-GPU platforms. Such hardware changes require the user to reconsider the parallel rendering algorithms. In this paper, we thoroughly investigate the NUMA-aware image compositing problem, which is the key final stage in sort-last parallel rendering. Based on a proven radix-k strategy, we find one optimal compositing algorithm, which takes advantage of NUMA architecture on the multi-GPU platform. We quantitatively analyze different image compositing modes for practical image compositing, taking into account peer-to-peer communication costs between GPUs. Our experiments on various datasets show that our image compositing method is very fast, an image of a few megapixels can be composited in about 10 ms by eight GPUs.     

On the Design, Development, Deployment, and Network Survivability Analysis of the Dynamic Routing System Protocol

With the ever-increasing demands on server applications, reliability is of paramount importance. Often these services are implemented using a distributed server cluster architecture where many servers act together providing end user services. We evaluated one hundred deployed systems and found that over a one-year period, thirteen percent of the hardware failures were network related. To reliably provide end-user services, the server clusters must guarantee server-to-server communication in the presence of these network failures. We describe a protocol designed to provide proactive dynamic routing for server clusters architectures called the Dynamic Routing System (DRS) protocol and present analysis to its survivability in the presence of network failure. Our experiments show that, for an eight-node server cluster with three concurrent network failures, the DRS provides a 267% improvement in the probability of server to server communication over a traditional network topology. Additionally, the proactive routing approach of the DRS performs better than traditional routing systems by fixing network problems before they affect application communication.     

The Connection Machine: PDE solution on 65 536 processors

The Connection Machine is a massively parallel architecture with 65 536 single-bit processors and 32 Mbytes of memory, organized as a high-dimensional hypercube. A sophisticated router system provides efficient communication between remote processors. A rich software environment, including a parallel extension of COMMON LISP, provides access to the processors and network. Virtual processor capability extends the degree of fine-grained parallelism beyond 1 000 000.We describe the hardware and the parallel programming environment. We then present implementations of SOR, Multigrid and Conjugate Gradient algorithms for solving Partial Differential Equations on the Connection Machine. Measurements of computational efficiency are provided as well as an analysis of opportunities for achieving better performance. Despite the lack of floating-point hardware, computation rates above 100 Mflops have been achieved in PDE solution. Virtual processors prove to be a real advantage, easing the effort of software development while improving system performance significantly.     

Mobile-IT Education (MIT. EDU): m-learning applications for classroom settings

Abstract In this paper, we describe the Mobile-IT Education (MIT.EDU) system, which demonstrates the potential of using a distributed mobile device architecture for rapid prototyping of wireless mobile multi-user applications for use in classroom settings. MIT.EDU is a stable, accessible system that combines inexpensive, commodity hardware, a flexible sensor/peripheral interconnection bus, and a powerful, light-weight distributed sensing, classification, and inter-process communications software architecture to facilitate the development of distributed real-time multi-modal and context-aware applications. We demonstrate the power and functionality of this platform by describing a number of MIT.EDU application deployments in educational settings. Initial evaluations of these experiments demonstrate the potential of using the system for real-world interactive m-learning applications.     

煤矿物联网统一通信平台的研究

提出了以TCP/IP协议为核心,高速工业以太网络为主干,无线局域网、无线传感网、现场总线和RS485总线为延伸,建设煤矿物联网统一通信平台的技术方案,重点阐述了煤矿物联网统一通信平台架构、关键设备、协议体系、虚拟存取及面向服务的通信平台架构的实现方法。     

ATR信息处理系统的软件总线应用

ATR系统的开发是插头插座式软件体系结构下的算法构件组装.为支持算法评估和选择,文章借鉴计算机硬件总线技术,提出了采用软件总线技术对算法构件进行集成,同时给出了具有形式化语义的消息模型.基于ATR支撑平台的ATR系统开发时可以进行算法评估和算法选择,在新的算法出现时不需要对平台进行修改.理论研究表明:软件总线为ATR支撑平台扩展、为通用平台提供了实现途径.     

Interprocedural Data Flow Based Optimizations for Distributed Memory Compilation

Data parallel languages like High Performance Fortran (HPF) are emerging as the architecture independent mode of programming distributed memory parallel machines. In this paper, we present the interprocedural optimizations required for compiling applications having irregular data access patterns, when coded in such data parallel languages. We have developed an Interprocedural Partial Redundancy Elimination (IPRE) algorithm for optimized placement of runtime preprocessing routine and collective communication routines inserted for managing communication in such codes. We also present two new interprocedural optimizations: placement of scatter routines and use of coalescing and incremental routines. We then describe how program slicing can be used for further applying IPRE in more complex scenarios. We have done a preliminary implementation of the schemes presented here using the Fortran D compilation system as the necessary infrastructure. We present experimental results from two codes compiled usng our system to demonstrate the efficacy of the presented schemes. ©1997 John Wiley & Sons, Ltd.     

Toward a hardware man-in-the-middle attack on PCIe bus

The growing need for high rate communication of recent embedded systems is leading to the adoption of the PCIe protocol (Peripheral Component Interconnect express) as an internal data bus. This technology is used in some recent smartphones, and will probably be adopted globally in the next few years. The communication between the processor (in the SoC) and its memory through the PCIe bus represents an important source of information for criminal investigations. In this paper, we present a new attack vector on PCIe based on a hardware Man-in-the-Middle. This system allows real-time data analysis, data-replay, and a copy technique inspired by the shadow-copy principle. Through this one, it is possible to locate, duplicate, and replay sensitive data. The main challenge here is to develop an architecture compliant with PCIe protocol constraints, such as response time, frequency, and throughput, in order to be non-detectable to the communication parts. We designed a proof of concept of an emulator based on a computer with PCIe 3.0 bus and a Stratix 5 FPGA with an endpoint PCIe port as a development target.     

基于HDLC协议的列车网络接口单元设计与实现

简要阐述HDLC网络基本通信原理的基础上,介绍了基于HDLC协议的列车网络接口单元的软硬件设计。硬件部分主要基于嵌入式CPCI总线和协议控制器SAB82532实现了通信网卡的设计;软件部分主要完成了HDLC通信网卡板级通道驱动软件和应用层通信软件的设计,并在此基础上,通过封装设计后的API驱动函数的调用,实现了实验室环境下HDLC通信测试功能。测试结果表明,设计的HDLC网络接口单元基本满足了通信要求,达到了预期目标。     

智能家庭控制系统接口访问机制研究

针对智能家庭控制系统,提出了基于中间通用适配层的接口访问机制,分离上层应用和底层硬件,将点对点的接口访问方式转化为总线式接口访问机制,并提供无缝集成底层网络和通信协议的接口.这种通用的接口访问机制将从根本上改变智能家庭控制系统的体系架构,使得核心控制单元能够非常灵活地满足用户应用需求和适配各种底层网络技术.     

A Distributed Scheduling Algorithm for Real-Time Communication on Slotted Shared Medium

Algorithms for arbitrating and scheduling transmissions from different transmitters sharing a common access medium arise often in the design of many shared and distributed systems. In this paper we present a distributed algorithm for arbitrating time-constrained transmissions on slotted shared access media. The two most important distinguishing features of our algorithm are: (1) unlike most of the other schemes that guarantee on-time transmission over shared media by centralized preallocation of slots, our algorithm is fully distributed and completely on-line; (2) it eliminates one of the common pitfalls of all slotted systems, that is, allocation in integral multiples of full slots. We derive sufficient conditions for schedulability and show that the proposed scheme achieves high levels of schedulable utilization. We also show that the schedulable utilization increases as the length of the allocation cycle increases and asymptotically approaches the maximum achievable utilization. We present a distributed slot access protocol to realize the proposed algorithm for ring architecture. The protocol can be easily modified for other topologies, such as bus and dual-bus networks. Using illustrative examples we demonstrate the effectiveness of the algorithm.     

Linux下EPP-CAN通信的设计及实现

介绍了EPP-CAN通信设计及实现方法，给出了硬件构成及其在Linux下C语言的软件结构。由于EPP模式并口是PC机的标准配置且传输速度较高，因此能有效发挥CAN的高效快速数据传输特性。该方法为使用PC机直接、高效访问CAN总线提供了极大的便利。     

一种基于485标准总线的工业控制系统架构

在工程应用领域,由于485标准总线硬件设计简单,控制方便,成本低廉而得到广泛应用,但也存在一些不足。针对传统485标准总线结构的缺陷,提出了新的通用型系统总线结构。这种结构从控制设备来分由主控设备、分控设备、从设备组成,特别提出了双CPU＋信息交换池技术,重点解决工程应用中普遍存在的由于任务多、设备分布广、通讯距离远等带来的各种困难,使传统485标准总线的功能得到大大增强,基本上满足相对复杂条件下的使用。