Amorphous silicon buried-channel thin-film transistors

We demonstrate a buried-channel thin-film field effect transistor (TFT) based on deposited silicon nitride and hydrogenated amorphous silicon with the conducting channel recessed approximately 50 Å from the interface. We fabricate transistors and capacitors by DC reactive magnetron sputtering of a silicon target in a plasma of (Ar+H ₂+N₂) or (Ar+H₂) for the nitride and silicon layers, respectively. To create a step in the conduction band, and thus a buried-channel, we vary the hydrogen partial pressure which varies the hydrogen content and the bandgap of amorphous silicon. Capacitance-voltage and current-voltage measurements on these devices present strong evidence for the existence of the buried-channel. We achieve a record field effect mobility in saturation of 1.68 cm² /V-s with amorphous silicon deposited at 230°C, and an acceptable mobility of 0.44 cm²/V-s with amorphous silicon deposited at 125°C     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

Formation of source and drain regions for a-Si:H thin-filmtransistors by low-energy ion doping technique

A low-energy ion doping technique has been applied to form source and drain regions of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) with an inverted staggered electrode structure. Phosphine gas diluted in hydrogen was discharged by RF power and magnetic field. Both phosphorus and hydrogen ions were accelerated to an energy of 5.5 keV and implanted into heated samples. The ON-OFF current ratio and the field-effect mobility of the fabricated TFTs were 10⁶ and 0.12 cm²/V-s, respectively     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Improvement of Hydrogenated Amorphous-Silicon TFT Performances With Low-$k$Siloxane-Based Hydrogen Silsesquioxane (HSQ) Passivation Layer

A low-dielectric-constant (low-k)-material siloxane-based hydrogen silsesquioxane (HSQ) is investigated as a passivation layer in bottom-gate hydrogenated amorphous-silicon thin-film transistors (a-Si : H TFTs). The low-k HSQ film passivated on TFT promotes the brightness and aperture ratio of TFT liquid-crystal display due to its high light transmittance and good planarization. In addition, the performance of a-Si : H TFT with HSQ passivation has been improved, compared to a conventional silicon nitride (SiN_x)-passivated TFT because the hydrogen bonds of HSQ assist the hydrogen incorporation to eliminate the density of states between the back channel and passivation layer. Experimental results exhibit an improved field-effect mobility of 0.57 cm²/Vmiddots and a subthreshold swing of 0.68 V     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

KrF excimer laser annealed TFT with very high field-effect mobilityof 329 cm2/V-s

A thin-film transistor (TFT) with a maximum field-effect mobility of 320 cm²/V-s, an on/off current ratio of 7.6×10⁷ , a threshold voltage of 6.7 V and a subthreshold slope of 0.37 V/decade was fabricated by using pulse laser annealing processes. Amorphous silicon films (a-Si:H) with a very low impurity concentration of 4×10¹⁸ cm^-3 for oxygen, 1.5×10¹⁸ cm^-3 for carbon, and 2×10¹⁷ cm^-3 for nitrogen were deposited by a plasma chemical vapor deposition (CVD) method and annealed by KrF excimer laser (wavelength of 248 nm). The Raman spectroscopy technique was a useful tool for optimizing laser annealing conditions. Experimental results show that two factors are very important for fabricating very-high mobility TFTs: (1) utilizing high-purity as-deposited a-Si:H film; and (2) performing whole laser annealing processes sequentially in a vacuum container and optimizing illumination conditions     

Amorphous-silicon thin-film transistors with very high field-effectmobility

The fabrication and performance of hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with field-effect mobilities of 5.1 cm²/V-s are discussed. This is the highest field-effect mobility of this type of TFT reported to date. The device shows an on/off current ratio exceeding 10⁵ and a subthreshold swing of 0.5 V/decade     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.