ESD protection design for I/O libraries in advanced CMOS technologies

There are several approaches for ESD protection of integrated circuits. This paper provides practical guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR, MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special CDM ESD protection solutions are not considered.     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

Circuit and process design considerations for ESD protection in advanced CMOS processes

This paper reviews many of the important issues for building ESD protection with NMOS transistors containing silicided diffusions and lightly doped drain junctions. The impact of device process parameters, such as gate length, side-wall spacer and silicided, graded junctions, on NMOS ESD performance are discussed. More recent process advances, such as LATID and halo implants, are also reviewed. Several varieties of circuits for triggering NMOS protection transistors under ESD conditions are covered.     

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R_ON * C_ESD, I_CP/C_ESD, V_HBM/C_ESD, and I_CP/A_Layout) of ESD protection diodes with new proposed layout styles can be successfully improved.     

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.     

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35 /spl mu/m CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original /spl sim/2 kV to >8 kV by using this proposed ESD protection circuit.     

一种CMOS工艺高速端口的ESD保护设计

随着CMOS工艺的不断深化,CMOS器件开启速度越来越快,有利于设计出更高速的电路及相关接口器件。但随着CMOS工艺深化的同时,器件的栅氧厚度也越来越薄,栅氧的击穿电压大大降低,使得器件更容易受到ESD损伤。采用传统的ESD结构会显著增加节点电容,节点电容的增加会限制电路接口速率的增加。采用中芯国际(SMIC)0.13μm工艺,设计实现了一种ESD保护电路,I/O端口翻转速率达到2 Gbps,对人体模型耐压达到2000 V。经过仿真验证、流片验证,设计的结构达到了该芯片抗静电能力以及端口高速传输速率的要求。     

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.     

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle.     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.     

Optimized ESD protection circuits for high-speed MOS/VLSI

New electrostatic discharge (ESD) protection circuits for MOPS/VLSI provide typical 2.7-ns delays and protection against voltage spikes up to 2200 V (limit of test circuit) in some cases. These circuits contain some traditional elements plus new features including a gate-drain connected thin-oxide device to achieve the very low protected node voltage (~2 V) required for advanced thin gate oxide technologies. In addition, for CMOS application, these all-NMOS (or PMOS) circuits would offer a high degree of latchup immunity. For both positive and negative spikes, single-pulse and repeated-pulse test data were obtained for six different test conditions. Electrical and physical analyses show dominant failure modes. Because techniques used to improve protection tend to degrade speed, a figure of merit is proposed to assist a fair comparison between different ESD protection circuit designs.     

Structures for ESD protection in CMOS processes

This paper reviews the basic building blocks that are used for CMOS ESD protection structures, circuit and layout effects are considered. The performance of several structures is characterized in order to demonstrate the different effects. Guide-lines and recommendations for proper protection structure implementation are given.     

Technology design for high current and ESD robustness in a deepsubmicron CMOS process

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 μm and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS

A fully integrated system-on-a-chip (SOC) in 130-nm CMOS technology compliant with world-band 802.11a/b/g is presented. This SOC integrates all blocks including 2.4-GHz/5-GHz RF tranceiver, baseband physical layer (PHY), and the medium access controller (MAC). At 1.8 V, the whole SOC dissipates 144/168 mA in receiving mode and 114/150 mA in transmitting mode for 2.4-GHz/5-GHz-band operations. The measured receiver sensitivity at 2.4 GHz/5 GHz is $-{hbox{77.5}}/-{hbox{74}} hbox{dBm}$ at 54 Mb/s rate, and the transmitter EVM at 54 Mb/s rate is $-{hbox{33}}/-{hbox{30}} {hbox {dB}}$ at an output power of $-{hbox{7}}/-{hbox{8}} hbox{dBm}$. By integrating multiple on-chip LDOs with no off-chip capacitors, this SOC features the capability of being directly supplied by off-chip switching-type DC/DC converter without performance degradation.      

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

Distributed ESD protection for high-speed integrated circuits

Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme could limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device