Reliability study of board-level lead-free interconnections under sequential thermal cycling and drop impact

The sequential thermal cycling (TC) and drop impact test are more reasonable to evaluate the reliability of lead-free solder interconnections compared with separate TC test or drop impact test. In this paper, sequential TC (−40 °C/125 °C, 13 min of soak time, 12 min of dwell time, totally 50 min of cycle time) and drop impact test (a sine impact pulse with a peak acceleration of 1500g and a duration time of 0.5 ms) were conducted to study the failure mechanism of solder interconnections under sequential TC and drop impact test. The TC load has larger effect on the Cu/solder interface at the PCB side than that of Ni (P)/solder interface at the component side. For the thermally cycled samples, the failure location of solder interconnections under drop impact has changed from initiation and propagation along the thin reaction layer (mode 1) between intermetallic compound (IMC) layer and Ni (P) pad at the component side to initiation at the bulk solder and propagation along the Cu₃Sn IMC layer (mode 2) or entirely through the bulk solder (mode 3) at the PCB side. The failure mechanism has also changed from the entirely brittle crack to the mixture of fatigue crack and brittle crack.     

A novel impact test system for more efficient reliability testing

Portable electronic products such as mobile phones experience various loadings in their use environments but accidental drops are encountered most frequently. Over the past few years the drop reliability of electronic assemblies has been studied by means of the travelling table test apparatuses described in the JESD22-B111 drop test standard. There are, however, a few essential shortcomings related to this approach: for example, (1) testing can be time-consuming as a result of the low impact repetition frequency (0.1 Hz) characteristic of the approach; (2) the peak deceleration amplitude varies from one pulse to another; (3) packages placed at different locations on the printed wiring board experience highly dissimilar loading conditions, and (4) the lifetime of a particular location varies significantly from one board to another. In order to overcome these shortcomings an alternative impact test method is presented in this paper. The new method is based on the use of a pneumatic cylinder to produce the desired shock pulses, for example those defined in the JESD22-B110A and JESD22-B111 standards. The measurements showed that the pneumatic test system is capable of producing peak deceleration well above the maximum (2900 G) stated in the JESD22-B110A. More importantly, a testing time an order of magnitude shorter was achieved by increasing the drop impact repetition frequency; an impact repetition frequency of 1.6 Hz was achieved with the pneumatic shock impact tester. Two improved component board attachments based on the support of the full board width were designed in order to simplify the bending motion of component boards. Both the finite element calculations and the experimental results showed that under the full board width support conditions the bending of the component board is more uniform and different component locations experience more equal strains as compared to bending under the conventional 4-point support conditions. The reliability tests that were performed verified that the full board width support produces the same failure modes and that the lifetimes of packages at different locations on the printed wiring board are more comparable with each other with the full board width support than they are with the conventional 4-point support. The benefits of the pneumatic tester that was developed are related to the time needed for testing, the stability of the impact pulse over long periods of time, and the more consistent lifetime statistics achieved by the simplified bending of the component board during testing.     

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.     

Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

We investigate in this paper board-level drop reliability of chip-scale packages subjected to JEDEC drop test condition B, which features an impact pulse profile with a peak acceleration of 1500G and a pulse duration of 0.5 ms. Effects of Sn–Ag–Cu or Sn–Pb solder joint compositions, fluxes, and substrate pads with Ni/Au surface finish or OSP coating on the drop reliability of the board-level test vehicle are compared. Locations and modes of the failed solder joints are examined using the dye stain test. The results indicate that solder joints with a low Ag weight content and substrate pads with OSP coating both enhance the drop resistance of the board-level test vehicle.     

Joint reliability evaluation of thermo-compression bonded FPCB/RPCB joints under high temperature storage test

In this study, electrodes on a flexible printed circuit board (FPCB) and rigid printed circuit board (RPCB) were bonded by a thermo-compression bonding. Pb-free Sn–3.0Ag–0.5Cu solder was used as an interlayer. In order to determine the optimum bonding conditions for bonding pressure and time, a 90° peel test of the FPCB–RPCB joint was conducted. The relationships between the bonding conditions, interfacial reactions, and peel strength were investigated. The optimum bonding pressure and time were 2.04 MPa and 5 s at 260 °C, respectively. Thin and uniform (Ni,Cu)₃Sn₄ intermetallic compound (IMC) layers formed at both FPCB/Sn–3.0Ag–0.5Cu/RPCB interfaces. In a high temperature storage (HTS) test of 125 °C, the peel strength decreased as the aging time increased. After the HTS test, brittle interfaces formed in the PCB joints, resulting in the switching of the failure mode from a polyimide–electrode failure to a brittle IMC failure.     

Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events

The purpose of this study is to establish a predictive fatigue life model for SAC 105 (Sn-1.0Ag-0.5Cu) and SAC 1205N (Sn-1.2Ag-0.5Cu with nickel) lead-free solder alloys. A simulation model approach was developed to investigate the stress and strain of the solder joint during drop tests. A Joint Electronic Device Engineering Council (JEDEC) Condition B drop test was simulated. This test is characterized by a 1500g peak acceleration for an impulse duration of 0.5 ms. At the point of impact during the drop test, the deformation of the printed circuit board (PCB) via bending and mechanical shocks can cause joint cracks in the solder. To establish a predictive model for the 10% fatigue life of the lead-free solder joint under drop test conditions, the study was conducted in three main phases: material analysis of the lead-free solder alloy, the drop test model, and the 10% fatigue life analysis. Tensile tests of SAC 105 and SAC 1205N were used to examine the elastic and plastic behavior of the solder alloy mechanism. Simulations and drop tests were performed to investigate the failure of the microelectronic package resulting from the drop test. The predictive fatigue life models of SAC 105 and SAC 1205N were validated by the experimental results with satisfactory accuracy.     

Effects of different drop test conditions on board-level reliability of chip-scale packages

In this study, reliability performances of board-level chip-scale packages subjected to four JEDEC drop test conditions: A (500 G; 1.0 ms), B (1500 G; 0.5 ms), F (900 G; 0.7 ms), and H (2900 G; 0.3 ms) were evaluated experimentally and numerically. For each of the test conditions, over 80% of the failed solder joints fractured on the package side. Among the four test conditions, condition A led to the best drop resistance while condition H the worst. Though drop resistances resulted from conditions B and F were close to each other, the former contained a greater portion of failure identified as test board pad peeling. Numerical solutions of interfacial stresses, obtained by the transient finite element analysis, provided a supporting basis for the crack propagation observed from the experiments, for which the crack initiated from the inner corner of the solder joint on the package side and propagated outwards. The strain rates were found to be within 10² s⁻¹ for the four drop test conditions. Using computed maximum interfacial normal and shear stresses, a fatigue reliability model that predicts the drop counts for different drop test conditions was established.     

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L₉ (3⁴) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.     

Advanced analysis on board trace reliability of WLCSP under drop impact

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSP^nl™), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSP^nl can exhibit distinct failure modes under different test board and/or CSP^nl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability.     

Measuring stress next to Au ball bond during high temperature aging

A real-time signal of the stress caused by a ball bond is recorded during long-term high temperature storage (HTS) without destroying the ball bond, using a piezoresistive integrated CMOS microsensor located next to the Al bond pad (test pad) on a test chip. The sensor is sensitive to in-plane shear stress changes Δτ_xy that arise due to tensile or compressive stress at the test pad. While performing HTS at 200 °C during 400 h, significantly different stress signals are observed with a ball bond (test structure) compared to those observed without a ball bond (reference structure). Simultaneous to Δτ_xy the contact resistance of the bond was directly measured with a four-wire method in which two connection paths lead to the test pad and a second wire bond is made on top of the test ball bond. The contact resistance values measured at room temperature (25 °C) before and after HTS are 2.1 mΩ and 6.1 mΩ, respectively. Effects influencing the stress signal during HTS include volume changes by the growth of intermetallics. The stress increase initially observed during HTS shows bond shrinking corresponding to growth of Au-rich phases which was previously reported to result in volume shrinkage. A subsequent phase of signal drop is observed starting after 200 h, indicating the presence of a different mechanism partly reducing the stress built up previously, and attributed to lateral growth of Al-rich intermetallics, partially consuming the pad Al outside the bond region, and resulting in volume expansion. Finite element models are developed to support the interpretation of the stress signal features. One of the models simulates the shrinking of Au-Al material due to phase transformation. When calibrated to experimental data, the peak underpad Tresca stress level generated during such contraction is 53 MPa, located 2.4 μm inside of the 55 μm diameter bond zone.     

Evaluation of the drop response of handheld electronic products

The aim of the product level drop response evaluation presented in this paper is to provide goals and guidelines for the development of a board-level drop test methodology that would better reproduce the field use loading conditions of modern portable electronic devices. Eight commercially available smart phones from different manufacturers were evaluated for their free-fall drop response. For this purpose, miniature accelerometer and strain gauges were attached to various locations on the component board inside the product covers. The maximum strain, average rate to maximum strain, frequency of the effective mode shapes, and maximum deceleration were determined from the measured strain and deceleration histories. The determined values showed significant variation from drop to another and device to another, but it was noteworthy that the extreme magnitude of the strain, average rate to maximum strain, and deceleration can be very high: values as high as 10,000 μ (“micro-strain” = [10⁻⁶ m/m]), 26 s⁻¹, and 10 kG were measured, respectively.     

Corner bonding of CSPs: processing and reliability

The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Failure Analysis of Board-Level Sn-Ag-Cu Solder Interconnections Under JEDEC Standard Drop Test

This work investigates the board-level drop reliability of printed circuit boards (PCBs) assembled using three chip-size packages subjected to Joint Electron Device Engineering Council (JEDEC) standard drop test condition B. The acceleration and dynamic strain responses at several locations of the board-level package in the time and frequency domain are comprehensively investigated. The results in the time domain suggest that the dynamic response of the board-level package has two phases: forced vibration and free vibration. The maximum response occurs at the first half free vibration cycle. The acceleration response at the center of the PCB is larger than at the edges, whereas the dynamic strain response is just the opposite. The results in the frequency domain show that the first mode is fundamental. In addition, failure analysis is performed using the dye-and-pry test and cross-section test, suggesting that the brittle cracking occurs at the layer between the integrated circuit (IC) pad and the solder, not only through intermetallic compound (IMC) but also along the surface between the IC pad and IMC.     

板级跌落碰撞下无铅焊点的可靠性研究

文中引入一块不同于JEDEC标准测试板的圆形测试板,探究板级跌落碰撞下无铅焊点的可靠性.首先做模态试验了解测试板的动力学特性,接着做跌落测试,同时测量板的应变和加速度历程.并用ABAQUS软件进行模拟,模拟焊点在跌落碰撞条件下焊点的应力应变等.结果表明有限元模拟得到的应变、板中心的加速度响应和试验吻合,而且用模拟预测的失效焊点的位置与试验一致.失效模式是靠近封装一侧的金属间化合物(IMC)界面的脆性断裂.     

A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables     

Reduction of ultrasonic pad stress and aluminum splash in copper ball bonding

Given the cost and performance advantages associated with Cu wire, it is being increasingly seen as a candidate to replace Au wire for making interconnections in first level microelectronics packaging. A Cu ball bonding process is optimized with reduced pad stress and splash, using a 25.4 μm diameter Cu wire. For ball bonds made with conventionally optimized bond force and ultrasonic settings, the shear strength is ≈140 MPa. The amount of splash extruding out of bonded ball interface is between 10 and 12 μm. It can be reduced to 3-7 μm if accepting a shear strength reduction to 50-70 MPa. For excessive ultrasonic settings, elliptical shaped Cu bonded balls are observed, with the minor axis of the ellipse in the ultrasonic direction and the major axis perpendicular to the ultrasonic direction. To quantify the direct effect of bond force and ultrasound settings on pad stress, test pads with piezoresistive microsensors integrated next to the pad and the real-time ultrasonic force signals are used. By using a lower value of bond force combined with a reduced ultrasound level, the pad stress can be reduced by 30% while achieving an average shear strength of at least 120 MPa. These process settings also aid in reducing the amount of splash by 4.3 μm.     

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

Impact of Thermal Cycling on Sn-Ag-Cu Solder Joints and Board-Level Drop Reliability

The electronic packaging industry uses electroless nickel immersion gold (ENIG) or Cu-organic solderability preservative (Cu-OSP) as a bonding pad surface finish for solder joints. In portable electronic products, drop impact tests induce solder joint failures via the interfacial intermetallic, which is a serious reliability concern. The intermetallic compound (IMC) is subjected to thermal cycling, which negatively affects the drop impact reliability. In this work, the reliability of lead-free Sn-3.0Ag-0.5Cu (SAC) soldered fine-pitch ball grid array assemblies were investigated after being subjected to a combination of thermal cycling followed by board level drop tests. Drop impact tests conducted before and after thermal aging cycles (500, 1000, and 1500 thermal cycles) show a transition of failure modes and a significant reduction in drop durability for both SAC/ENIG and SAC/Cu-OSP soldered assemblies. Without thermal cycling aging, the boards with the Cu-OSP surface finish exhibit better drop impact reliability than those with ENIG. However, the reverse is true if thermal cycle (TC) aging is performed. For SAC/Cu-OSP soldered assemblies, a large number of Kirkendall voids were observed at the interface between the intermetallic and Cu pad after thermal cycling aging. The void formation resulted in weak bonding between the solder and Cu, leading to brittle interface fracture in the drop impact test, which resulted in significantly lower drop test lifetimes. For SAC/ENIG soldered assemblies, the consumption of Ni in the formation of NiCuSn intermetallics induced vertical voids in the Ni(P) layer.